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When invoking a signal handler for an ARM target, make sure the IT bits in the CPSR are cleared. (This would otherwise cause incorrect execution if the IT state was non-zero when an exception occured. This bug has been masked previously because we weren't getting the IT state bits at exception entry right anyway.) Also use the proper cpsr_read()/cpsr_write() interface to update the CPSR rather than manipulating CPUState fields directly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Read the documentation in qemu-doc.html. Fabrice Bellard.