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linux-user: ARM: clear the IT bits when invoking a signal handler

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When invoking a signal handler for an ARM target, make sure the IT
bits in the CPSR are cleared. (This would otherwise cause incorrect
execution if the IT state was non-zero when an exception occured.
This bug has been masked previously because we weren't getting the
IT state bits at exception entry right anyway.)

Also use the proper cpsr_read()/cpsr_write() interface to update
the CPSR rather than manipulating CPUState fields directly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-01-14 20:39:19 +01:00 committed by Aurelien Jarno
parent bc4a0de0a2
commit 964413d9d9
1 changed files with 9 additions and 7 deletions
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16
linux-user/signal.c
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@ -1256,6 +1256,14 @@ setup_return(CPUState *env, struct target_sigaction *ka,
abi_ulong handler = ka->_sa_handler;
abi_ulong retcode;
int thumb = handler & 1;
uint32_t cpsr = cpsr_read(env);
cpsr &= ~CPSR_IT;
if (thumb) {
cpsr |= CPSR_T;
} else {
cpsr &= ~CPSR_T;
}
if (ka->sa_flags & TARGET_SA_RESTORER) {
retcode = ka->sa_restorer;
@ -1278,13 +1286,7 @@ setup_return(CPUState *env, struct target_sigaction *ka,
env->regs[13] = frame_addr;
env->regs[14] = retcode;
env->regs[15] = handler & (thumb ? ~1 : ~3);
env->thumb = thumb;
#if 0
#ifdef TARGET_CONFIG_CPU_32
env->cpsr = cpsr;
#endif
#endif
cpsr_write(env, cpsr, 0xffffffff);
return 0;
}