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Peter Maydell 552fda48e0 MIPS patches queue 
- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
 - Various Toshiba TX79 opcodes implemented
 - Rewrite UHI errno_mips() using switch statement
 - Few fixes and improvements in the SONIC model (dp8393x)
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Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)

# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210711:
  dp8393x: don't force 32-bit register access
  dp8393x: Rewrite dp8393x_get() / dp8393x_put()
  dp8393x: Store CAM registers as 16-bit
  dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
  dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
  dp8393x: fix CAM descriptor entry index
  target/mips: Rewrite UHI errno_mips() using switch statement
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
  hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
  hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-12 15:58:17 +01:00
..
sysemu target/mips: Move CP0 helpers to sysemu/cp0.c 2021-05-02 16:49:35 +02:00
tcg MIPS patches queue 2021-07-12 15:58:17 +01:00
cpu-defs.c.inc target/mips: Remove vendor specific CPU definitions 2021-01-14 17:13:54 +01:00
cpu-param.h target/mips: Support variable page size 2020-06-01 13:28:21 +02:00
cpu-qom.h target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed 2021-05-26 15:33:59 -07:00
cpu.c target/mips: Optimize regnames[] arrays 2021-06-24 16:48:08 +02:00
cpu.h target/mips: Restrict some system specific declarations to sysemu 2021-06-24 16:48:07 +02:00
fpu_helper.h target/mips: Set set_default_nan_mode with set_snan_bit_is_one 2021-05-16 07:13:51 -05:00
fpu.c target/mips: Optimize CPU/FPU regnames[] arrays 2021-05-02 16:49:34 +02:00
gdbstub.c target/mips: Extract FPU helpers to 'fpu_helper.h' 2021-01-14 17:13:53 +01:00
helper.h target/mips: Move TCG source files under tcg/ sub directory 2021-05-02 16:49:35 +02:00
internal.h target/mips: Optimize regnames[] arrays 2021-06-24 16:48:08 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_mips.h hw/mips: Implement the kvm_type() hook in MachineClass 2020-06-27 19:35:39 +02:00
kvm.c sysemu: Let VMChangeStateHandler take boolean 'running' argument 2021-03-09 23:13:57 +01:00
meson.build target/mips: Move TCG source files under tcg/ sub directory 2021-05-02 16:49:35 +02:00
mips-defs.h target/mips: Remove vendor specific CPU definitions 2021-01-14 17:13:54 +01:00
msa.c target/mips: Move msa_reset() to new source file 2021-05-02 16:49:34 +02:00
TODO Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00