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MIPS patches queue

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- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
 - Various Toshiba TX79 opcodes implemented
 - Rewrite UHI errno_mips() using switch statement
 - Few fixes and improvements in the SONIC model (dp8393x)
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Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)

# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210711:
  dp8393x: don't force 32-bit register access
  dp8393x: Rewrite dp8393x_get() / dp8393x_put()
  dp8393x: Store CAM registers as 16-bit
  dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
  dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
  dp8393x: fix CAM descriptor entry index
  target/mips: Rewrite UHI errno_mips() using switch statement
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
  hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
  hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-07-12 15:58:16 +01:00
commit 552fda48e0
10 changed files with 526 additions and 157 deletions
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2
MAINTAINERS
View File

@ -1304,7 +1304,7 @@ S: Maintained
F: hw/ppc/prep.c
F: hw/ppc/prep_systemio.c
F: hw/ppc/rs6000_mc.c
F: hw/pci-host/prep.[hc]
F: hw/pci-host/raven.c
F: hw/isa/i82378.c
F: hw/isa/pc87312.c
F: hw/dma/i82374.c

208
hw/net/dp8393x.c
View File

@ -85,6 +85,7 @@ static const char *reg_names[] = {
#define SONIC_MPT 0x2e
#define SONIC_MDT 0x2f
#define SONIC_DCR2 0x3f
#define SONIC_REG_COUNT 0x40
#define SONIC_CR_HTX 0x0001
#define SONIC_CR_TXP 0x0002
@ -157,12 +158,11 @@ struct dp8393xState {
MemoryRegion mmio;
/* Registers */
uint8_t cam[16][6];
uint16_t regs[0x40];
uint16_t cam[16][3];
uint16_t regs[SONIC_REG_COUNT];
/* Temporaries */
uint8_t tx_buffer[0x10000];
uint16_t data[12];
int loopback_packet;
/* Memory access */
@ -219,34 +219,48 @@ static uint32_t dp8393x_wt(dp8393xState *s)
return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
}
static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
static uint16_t dp8393x_get(dp8393xState *s, hwaddr addr, int offset)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint16_t val;
if (s->big_endian) {
val = be16_to_cpu(s->data[offset * width + width - 1]);
if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
addr += offset << 2;
if (s->big_endian) {
val = address_space_ldl_be(&s->as, addr, attrs, NULL);
} else {
val = address_space_ldl_le(&s->as, addr, attrs, NULL);
}
} else {
val = le16_to_cpu(s->data[offset * width]);
addr += offset << 1;
if (s->big_endian) {
val = address_space_lduw_be(&s->as, addr, attrs, NULL);
} else {
val = address_space_lduw_le(&s->as, addr, attrs, NULL);
}
}
return val;
}
static void dp8393x_put(dp8393xState *s, int width, int offset,
uint16_t val)
static void dp8393x_put(dp8393xState *s,
hwaddr addr, int offset, uint16_t val)
{
if (s->big_endian) {
if (width == 2) {
s->data[offset * 2] = 0;
s->data[offset * 2 + 1] = cpu_to_be16(val);
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
addr += offset << 2;
if (s->big_endian) {
address_space_stl_be(&s->as, addr, val, attrs, NULL);
} else {
s->data[offset] = cpu_to_be16(val);
address_space_stl_le(&s->as, addr, val, attrs, NULL);
}
} else {
if (width == 2) {
s->data[offset * 2] = cpu_to_le16(val);
s->data[offset * 2 + 1] = 0;
addr += offset << 1;
if (s->big_endian) {
address_space_stw_be(&s->as, addr, val, attrs, NULL);
} else {
s->data[offset] = cpu_to_le16(val);
address_space_stw_le(&s->as, addr, val, attrs, NULL);
}
}
}
@ -270,34 +284,28 @@ static void dp8393x_update_irq(dp8393xState *s)
static void dp8393x_do_load_cam(dp8393xState *s)
{
int width, size;
uint16_t index = 0;
uint16_t index;
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
address_space_read(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1],
s->cam[index][2], s->cam[index][3],
s->cam[index][4], s->cam[index][5]);
index = dp8393x_get(s, dp8393x_cdp(s), 0) & 0xf;
s->cam[index][0] = dp8393x_get(s, dp8393x_cdp(s), 1);
s->cam[index][1] = dp8393x_get(s, dp8393x_cdp(s), 2);
s->cam[index][2] = dp8393x_get(s, dp8393x_cdp(s), 3);
trace_dp8393x_load_cam(index,
s->cam[index][0] >> 8, s->cam[index][0] & 0xff,
s->cam[index][1] >> 8, s->cam[index][1] & 0xff,
s->cam[index][2] >> 8, s->cam[index][2] & 0xff);
/* Move to next entry */
s->regs[SONIC_CDC]--;
s->regs[SONIC_CDP] += size;
index++;
}
/* Read CAM enable */
address_space_read(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
s->regs[SONIC_CE] = dp8393x_get(s, dp8393x_cdp(s), 0);
trace_dp8393x_load_cam_done(s->regs[SONIC_CE]);
/* Done */
@ -313,14 +321,12 @@ static void dp8393x_do_read_rra(dp8393xState *s)
/* Read memory */
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
address_space_read(&s->as, dp8393x_rrp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
s->regs[SONIC_CRBA0] = dp8393x_get(s, dp8393x_rrp(s), 0);
s->regs[SONIC_CRBA1] = dp8393x_get(s, dp8393x_rrp(s), 1);
s->regs[SONIC_RBWC0] = dp8393x_get(s, dp8393x_rrp(s), 2);
s->regs[SONIC_RBWC1] = dp8393x_get(s, dp8393x_rrp(s), 3);
trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
@ -416,28 +422,22 @@ static void dp8393x_do_receiver_disable(dp8393xState *s)
static void dp8393x_do_transmit_packets(dp8393xState *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
int width, size;
int tx_len, len;
uint16_t i;
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
while (1) {
/* Read memory */
size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
trace_dp8393x_transmit_packet(dp8393x_ttda(s));
address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, s->data, size);
tx_len = 0;
/* Update registers */
s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
s->regs[SONIC_TCR] = dp8393x_get(s, dp8393x_ttda(s), 1) & 0xf000;
s->regs[SONIC_TPS] = dp8393x_get(s, dp8393x_ttda(s), 2);
s->regs[SONIC_TFC] = dp8393x_get(s, dp8393x_ttda(s), 3);
s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s), 4);
s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s), 5);
s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s), 6);
/* Handle programmable interrupt */
if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
@ -459,15 +459,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
i++;
if (i != s->regs[SONIC_TFC]) {
/* Read next fragment details */
size = sizeof(uint16_t) * 3 * width;
address_space_read(&s->as,
dp8393x_ttda(s)
+ sizeof(uint16_t) * width * (4 + 3 * i),
MEMTXATTRS_UNSPECIFIED, s->data,
size);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s),
4 + 3 * i);
s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s),
5 + 3 * i);
s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s),
6 + 3 * i);
}
}
@ -500,22 +497,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
/* Write status */
dp8393x_put(s, width, 0,
s->regs[SONIC_TCR] & 0x0fff); /* status */
size = sizeof(uint16_t) * width;
address_space_write(&s->as, dp8393x_ttda(s),
MEMTXATTRS_UNSPECIFIED, s->data, size);
dp8393x_put(s, dp8393x_ttda(s), 0, s->regs[SONIC_TCR] & 0x0fff);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
size = sizeof(uint16_t) * width;
address_space_read(&s->as,
dp8393x_ttda(s)
+ sizeof(uint16_t) * width
* (4 + 3 * s->regs[SONIC_TFC]),
MEMTXATTRS_UNSPECIFIED, s->data,
size);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
s->regs[SONIC_CTDA] = dp8393x_get(s, dp8393x_ttda(s),
4 + 3 * s->regs[SONIC_TFC]);
if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
/* EOL detected */
break;
@ -591,8 +578,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
case SONIC_CAP1:
case SONIC_CAP0:
if (s->regs[SONIC_CR] & SONIC_CR_RST) {
val = s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg) + 1] << 8;
val |= s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg)];
val = s->cam[s->regs[SONIC_CEP] & 0xf][SONIC_CAP0 - reg];
}
break;
/* All other registers have no special contraints */
@ -602,15 +588,14 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
trace_dp8393x_read(reg, reg_names[reg], val, size);
return s->big_endian ? val << 16 : val;
return val;
}
static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int size)
{
dp8393xState *s = opaque;
int reg = addr >> s->it_shift;
uint32_t val = s->big_endian ? data >> 16 : data;
trace_dp8393x_write(reg, reg_names[reg], val, size);
@ -691,11 +676,16 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
}
}
/*
* Since .impl.max_access_size is effectively controlled by the it_shift
* property, leave it unspecified for now to allow the memory API to
* correctly zero extend the 16-bit register values to the access size up to and
* including it_shift.
*/
static const MemoryRegionOps dp8393x_ops = {
.read = dp8393x_read,
.write = dp8393x_write,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.impl.min_access_size = 2,
.endianness = DEVICE_NATIVE_ENDIAN,
};
@ -764,7 +754,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
dp8393xState *s = qemu_get_nic_opaque(nc);
int packet_type;
uint32_t available, address;
int width, rx_len, padded_len;
int rx_len, padded_len;
uint32_t checksum;
int size;
@ -777,10 +767,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
rx_len = pkt_size + sizeof(checksum);
if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
width = 2;
padded_len = ((rx_len - 1) | 3) + 1;
} else {
width = 1;
padded_len = ((rx_len - 1) | 1) + 1;
}
@ -801,11 +789,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Check for EOL */
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* Are we still in resource exhaustion? */
size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* Still EOL ; stop reception */
return -1;
@ -813,11 +797,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Link has been updated by host */
/* Clear in_use */
size = sizeof(uint16_t) * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
dp8393x_put(s, width, 0, 0);
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->data, size, 1);
dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
/* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
@ -846,8 +826,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Pad short packets to keep pointers aligned */
if (rx_len < padded_len) {
size = padded_len - rx_len;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)"\xFF\xFF\xFF", size, 1);
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
"\xFF\xFF\xFF", size);
address += size;
}
@ -871,32 +851,20 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Write status to memory */
trace_dp8393x_receive_write_status(dp8393x_crda(s));
dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
dp8393x_put(s, width, 1, rx_len); /* byte count */
dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_write(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED,
s->data, size);
dp8393x_put(s, dp8393x_crda(s), 0, s->regs[SONIC_RCR]); /* status */
dp8393x_put(s, dp8393x_crda(s), 1, rx_len); /* byte count */
dp8393x_put(s, dp8393x_crda(s), 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
dp8393x_put(s, dp8393x_crda(s), 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
dp8393x_put(s, dp8393x_crda(s), 4, s->regs[SONIC_RSC]); /* seq_no */
/* Check link field */
size = sizeof(uint16_t) * width;
address_space_read(&s->as,
dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, s->data, size);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
/* Clear in_use */
size = sizeof(uint16_t) * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
dp8393x_put(s, width, 0, 0);
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size);
dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
/* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
@ -972,7 +940,7 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
address_space_init(&s->as, s->dma_mr, "dp8393x");
memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
"dp8393x-regs", 0x40 << s->it_shift);
"dp8393x-regs", SONIC_REG_COUNT << s->it_shift);
s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
@ -983,11 +951,11 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_dp8393x = {
.name = "dp8393x",
.version_id = 0,
.minimum_version_id = 0,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField []) {
VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
VMSTATE_UINT16_2DARRAY(cam, dp8393xState, 16, 3),
VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
VMSTATE_END_OF_LIST()
}
};

2
hw/pci-host/Kconfig
View File

@ -6,7 +6,7 @@ config XEN_IGD_PASSTHROUGH
default y
depends on XEN && PCI_I440FX
config PREP_PCI
config RAVEN_PCI
bool
select PCI
select OR_IRQ

2
hw/pci-host/meson.build
View File

@ -13,7 +13,7 @@ pci_ss.add(when: 'CONFIG_REMOTE_PCIHOST', if_true: files('remote.c'))
pci_ss.add(when: 'CONFIG_SH_PCI', if_true: files('sh_pci.c'))
# PPC devices
pci_ss.add(when: 'CONFIG_PREP_PCI', if_true: files('prep.c'))
pci_ss.add(when: 'CONFIG_RAVEN_PCI', if_true: files('raven.c'))
pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
# NewWorld PowerMac
pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))

11
hw/pci-host/prep.c → hw/pci-host/raven.c
View File

@ -81,6 +81,8 @@ struct PRePPCIState {
#define BIOS_SIZE (1 * MiB)
#define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */
static inline uint32_t raven_pci_io_config(hwaddr addr)
{
int i;
@ -158,7 +160,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr,
uint8_t buf[4];
addr = raven_io_address(s, addr);
address_space_read(&s->pci_io_as, addr + 0x80000000,
address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
MEMTXATTRS_UNSPECIFIED, buf, size);
if (size == 1) {
@ -190,7 +192,7 @@ static void raven_io_write(void *opaque, hwaddr addr,
g_assert_not_reached();
}
address_space_write(&s->pci_io_as, addr + 0x80000000,
address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
MEMTXATTRS_UNSPECIFIED, buf, size);
}
@ -293,8 +295,9 @@ static void raven_pcihost_initfn(Object *obj)
address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
/* CPU address space */
memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
&s->pci_io);
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
&s->pci_io_non_contiguous, 1);
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,

2
hw/ppc/Kconfig
View File

@ -85,7 +85,7 @@ config PREP
imply PCI_DEVICES
imply TEST_DEVICES
select CS4231A
select PREP_PCI
select RAVEN_PCI
select I82378
select LSI_SCSI_PCI
select M48T59

24
target/mips/tcg/sysemu/mips-semi.c
View File

@ -74,25 +74,19 @@ enum UHIOpenFlags {
UHIOpen_EXCL = 0x800
};
/* Errno values taken from asm-mips/errno.h */
static const uint16_t host_to_mips_errno[] = {
[ENAMETOOLONG] = 78,
static int errno_mips(int host_errno)
{
/* Errno values taken from asm-mips/errno.h */
switch (host_errno) {
case 0: return 0;
case ENAMETOOLONG: return 78;
#ifdef EOVERFLOW
[EOVERFLOW] = 79,
case EOVERFLOW: return 79;
#endif
#ifdef ELOOP
[ELOOP] = 90,
case ELOOP: return 90;
#endif
};
static int errno_mips(int err)
{
if (err < 0 || err >= ARRAY_SIZE(host_to_mips_errno)) {
return EINVAL;
} else if (host_to_mips_errno[err]) {
return host_to_mips_errno[err];
} else {
return err;
default: return EINVAL;
}
}

16
target/mips/tcg/translate.c
View File

@ -1179,7 +1179,6 @@ enum {
enum {
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
@ -15166,11 +15165,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
}
}
static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
}
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
@ -16069,14 +16063,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
}
case OPC_MDMX:
/* MDMX: Not implemented. */
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS_R6);

34
target/mips/tcg/tx79.decode
View File

@ -13,6 +13,8 @@
&rtype rs rt rd sa
&itype base rt offset
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
@ -22,6 +24,8 @@
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
@ldst ...... base:5 rt:5 offset:16 &itype
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
@ -29,11 +33,41 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
# MMI0
PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
PCGTW 011100 ..... ..... ..... 00010 001000 @rs_rt_rd
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd
PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd
PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
# MMI1
PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd
PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd
PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd
PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
# MMI3
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
# SPECIAL
LQ 011110 ..... ..... ................ @ldst
SQ 011111 ..... ..... ................ @ldst

382
target/mips/tcg/tx79_translate.c
View File

@ -2,12 +2,14 @@
* Toshiba TX79-specific instructions translation routines
*
* Copyright (c) 2018 Fredrik Noring
* Copyright (c) 2021 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
#include "translate.h"
@ -114,6 +116,53 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
*/
static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
/* Lower half */
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_logic_i64(cpu_gpr[a->rd], ax, bx);
/* Upper half */
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/* Parallel Subtract Byte */
static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64);
}
/* Parallel Subtract Halfword */
static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64);
}
/* Parallel Subtract Word */
static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64);
}
/*
* Min/Max (4 instructions)
* ------------------------
@ -139,6 +188,30 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PNOR rd, rs, rt Parallel NOR
*/
/* Parallel And */
static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
}
/* Parallel Or */
static bool trans_POR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
}
/* Parallel Exclusive Or */
static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
}
/* Parallel Not Or */
static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
}
/*
* Shift (9 instructions)
* ----------------------
@ -164,6 +237,90 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PCEQW rd, rs, rt Parallel Compare for Equal Word
*/
static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
TCGCond cond, unsigned wlen)
{
TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
if (a->rd == 0) {
/* nop */
return true;
}
c0 = tcg_const_tl(0);
c1 = tcg_const_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
/* Lower half */
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
for (int i = 0; i < (64 / wlen); i++) {
tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen);
}
/* Upper half */
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
for (int i = 0; i < (64 / wlen); i++) {
tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
}
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
tcg_temp_free(bx);
tcg_temp_free(ax);
tcg_temp_free(c1);
tcg_temp_free(c0);
return true;
}
/* Parallel Compare for Greater Than Byte */
static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 8);
}
/* Parallel Compare for Equal Byte */
static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
}
/* Parallel Compare for Greater Than Halfword */
static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 16);
}
/* Parallel Compare for Equal Halfword */
static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
}
/* Parallel Compare for Greater Than Word */
static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 32);
}
/* Parallel Compare for Equal Word */
static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32);
}
/*
* LZC (1 instruction)
* -------------------
@ -177,6 +334,68 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* SQ rt, offset(base) Store Quadword
*/
static bool trans_LQ(DisasContext *ctx, arg_itype *a)
{
TCGv_i64 t0;
TCGv addr;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new_i64();
addr = tcg_temp_new();
gen_base_offset_addr(ctx, addr, a->base, a->offset);
/*
* Clear least-significant four bits of the effective
* address, effectively creating an aligned address.
*/
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
gen_store_gpr(t0, a->rt);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
gen_store_gpr_hi(t0, a->rt);
tcg_temp_free(t0);
tcg_temp_free(addr);
return true;
}
static bool trans_SQ(DisasContext *ctx, arg_itype *a)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv addr = tcg_temp_new();
gen_base_offset_addr(ctx, addr, a->base, a->offset);
/*
* Clear least-significant four bits of the effective
* address, effectively creating an aligned address.
*/
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
gen_load_gpr(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
tcg_temp_free(addr);
tcg_temp_free(t0);
return true;
}
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
@ -217,6 +436,141 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PEXTLW rd, rs, rt Parallel Extend Lower from Word
*/
/* Parallel Pack to Word */
static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 a0, b0, t0;
if (a->rd == 0) {
/* nop */
return true;
}
a0 = tcg_temp_new_i64();
b0 = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
gen_load_gpr(a0, a->rs);
gen_load_gpr(b0, a->rt);
gen_load_gpr_hi(t0, a->rt); /* b1 */
tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32);
gen_load_gpr_hi(t0, a->rs); /* a1 */
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
tcg_temp_free(t0);
tcg_temp_free(b0);
tcg_temp_free(a0);
return true;
}
static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_deposit_i64(dl, b, a, 32, 32);
tcg_gen_shri_i64(b, b, 32);
tcg_gen_deposit_i64(dh, a, b, 0, 32);
}
static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
/* Lower half */
for (int i = 0; i < 64 / (2 * wlen); i++) {
tcg_gen_deposit_i64(cpu_gpr[a->rd],
cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
tcg_gen_deposit_i64(cpu_gpr[a->rd],
cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}
/* Upper half */
for (int i = 0; i < 64 / (2 * wlen); i++) {
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/* Parallel Extend Lower from Byte */
static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
{
return trans_PEXTLx(ctx, a, 8);
}
/* Parallel Extend Lower from Halfword */
static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
{
return trans_PEXTLx(ctx, a, 16);
}
/* Parallel Extend Lower from Word */
static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/* Parallel Extend Upper from Word */
static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/*
* Others (16 instructions)
* ------------------------
@ -301,3 +655,31 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
return true;
}
/* Parallel Rotate 3 Words Left */
static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 ax;
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
return true;
}
ax = tcg_temp_new_i64();
tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
tcg_temp_free(ax);
return true;
}