8be6971b73
Previously if we didn't enable the MMU it would be enabled in the realize() function anyway. Let's ensure that if we don't want the MMU we disable it. We also don't need to enable the MMU as it will be enabled in realize() by default. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
612 lines
19 KiB
C
612 lines
19 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "qemu/ctype.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "fpu/softfloat-helpers.h"
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/* RISC-V CPU definitions */
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static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
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const char * const riscv_int_regnames[] = {
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"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
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"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
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"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
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"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
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"x28/t3", "x29/t4", "x30/t5", "x31/t6"
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};
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const char * const riscv_fpr_regnames[] = {
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"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
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"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
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"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
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"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
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"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
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"f30/ft10", "f31/ft11"
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};
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const char * const riscv_excp_names[] = {
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"misaligned_fetch",
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"fault_fetch",
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"illegal_instruction",
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"breakpoint",
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"misaligned_load",
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"fault_load",
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"misaligned_store",
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"fault_store",
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"user_ecall",
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"supervisor_ecall",
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"hypervisor_ecall",
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"machine_ecall",
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"exec_page_fault",
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"load_page_fault",
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"reserved",
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"store_page_fault",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"guest_exec_page_fault",
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"guest_load_page_fault",
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"reserved",
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"guest_store_page_fault",
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};
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const char * const riscv_intr_names[] = {
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"u_software",
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"s_software",
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"vs_software",
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"m_software",
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"u_timer",
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"s_timer",
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"vs_timer",
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"m_timer",
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"u_external",
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"vs_external",
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"h_external",
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"m_external",
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"reserved",
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"reserved",
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"reserved",
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"reserved"
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};
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static void set_misa(CPURISCVState *env, target_ulong misa)
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{
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env->misa_mask = env->misa = misa;
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}
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static void set_priv_version(CPURISCVState *env, int priv_ver)
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{
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env->priv_ver = priv_ver;
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}
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static void set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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static void set_resetvec(CPURISCVState *env, int resetvec)
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{
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#ifndef CONFIG_USER_ONLY
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env->resetvec = resetvec;
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#endif
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}
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static void riscv_any_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_11_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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#if defined(TARGET_RISCV32)
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static void riscv_base32_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, 0);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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static void rv32imacu_nommu_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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static void rv32imafcu_nommu_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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#elif defined(TARGET_RISCV64)
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static void riscv_base64_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, 0);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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static void rv64imacu_nommu_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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#endif
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static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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char **cpuname;
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cpuname = g_strsplit(cpu_model, ",", 1);
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typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
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oc = object_class_by_name(typename);
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g_strfreev(cpuname);
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g_free(typename);
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if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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int i;
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#if !defined(CONFIG_USER_ONLY)
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
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}
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#endif
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
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#ifndef CONFIG_USER_ONLY
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
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#ifdef TARGET_RISCV32
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
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#endif
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
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}
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#endif
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx,
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riscv_int_regnames[i], env->gpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, " %s %016" PRIx64,
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riscv_fpr_regnames[i], env->fpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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}
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}
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static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = value;
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = tb->pc;
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}
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static bool riscv_cpu_has_work(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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/*
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* Definition of the WFI instruction requires it to ignore the privilege
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* mode and delegation registers, but respect individual enables
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*/
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return (env->mip & env->mie) != 0;
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#else
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return true;
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#endif
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}
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void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->pc = data[0];
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}
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static void riscv_cpu_reset(DeviceState *dev)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(cs);
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
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CPURISCVState *env = &cpu->env;
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mcc->parent_reset(dev);
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#ifndef CONFIG_USER_ONLY
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env->priv = PRV_M;
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env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
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env->mcause = 0;
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env->pc = env->resetvec;
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#endif
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cs->exception_index = EXCP_NONE;
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env->load_res = -1;
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set_default_nan_mode(1, &env->fp_status);
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}
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static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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{
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#if defined(TARGET_RISCV32)
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info->print_insn = print_insn_riscv32;
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#elif defined(TARGET_RISCV64)
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info->print_insn = print_insn_riscv64;
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#endif
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}
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static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(dev);
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CPURISCVState *env = &cpu->env;
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
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int priv_version = PRIV_VERSION_1_11_0;
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target_ulong target_misa = 0;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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if (cpu->cfg.priv_spec) {
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if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
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priv_version = PRIV_VERSION_1_11_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
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priv_version = PRIV_VERSION_1_10_0;
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} else {
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error_setg(errp,
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"Unsupported privilege spec version '%s'",
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cpu->cfg.priv_spec);
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return;
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}
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}
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set_priv_version(env, priv_version);
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if (cpu->cfg.mmu) {
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set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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set_feature(env, RISCV_FEATURE_PMP);
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}
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/* If misa isn't set (rv32 and rv64 machines) set it here */
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if (!env->misa) {
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/* Do some ISA extension error checking */
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if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
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error_setg(errp,
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"I and E extensions are incompatible");
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return;
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}
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if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
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error_setg(errp,
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"Either I or E extension must be set");
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return;
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}
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if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
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cpu->cfg.ext_a & cpu->cfg.ext_f &
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cpu->cfg.ext_d)) {
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warn_report("Setting G will also set IMAFD");
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cpu->cfg.ext_i = true;
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cpu->cfg.ext_m = true;
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cpu->cfg.ext_a = true;
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cpu->cfg.ext_f = true;
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cpu->cfg.ext_d = true;
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}
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/* Set the ISA extensions, checks should have happened above */
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if (cpu->cfg.ext_i) {
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target_misa |= RVI;
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}
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if (cpu->cfg.ext_e) {
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target_misa |= RVE;
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}
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if (cpu->cfg.ext_m) {
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target_misa |= RVM;
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}
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if (cpu->cfg.ext_a) {
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target_misa |= RVA;
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}
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if (cpu->cfg.ext_f) {
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target_misa |= RVF;
|
|
}
|
|
if (cpu->cfg.ext_d) {
|
|
target_misa |= RVD;
|
|
}
|
|
if (cpu->cfg.ext_c) {
|
|
target_misa |= RVC;
|
|
}
|
|
if (cpu->cfg.ext_s) {
|
|
target_misa |= RVS;
|
|
}
|
|
if (cpu->cfg.ext_u) {
|
|
target_misa |= RVU;
|
|
}
|
|
if (cpu->cfg.ext_h) {
|
|
target_misa |= RVH;
|
|
}
|
|
|
|
set_misa(env, RVXLEN | target_misa);
|
|
}
|
|
|
|
riscv_cpu_register_gdb_regs_for_features(cs);
|
|
|
|
qemu_init_vcpu(cs);
|
|
cpu_reset(cs);
|
|
|
|
mcc->parent_realize(dev, errp);
|
|
}
|
|
|
|
static void riscv_cpu_init(Object *obj)
|
|
{
|
|
RISCVCPU *cpu = RISCV_CPU(obj);
|
|
|
|
cpu_set_cpustate_pointers(cpu);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_riscv_cpu = {
|
|
.name = "cpu",
|
|
.unmigratable = 1,
|
|
};
|
|
|
|
static Property riscv_cpu_properties[] = {
|
|
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
|
|
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
|
|
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
|
|
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
|
|
DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
|
|
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
|
|
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
|
|
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
|
|
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
|
|
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
|
|
/* This is experimental so mark with 'x-' */
|
|
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
|
|
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
|
|
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
|
|
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
|
|
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
|
|
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
|
|
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void riscv_cpu_class_init(ObjectClass *c, void *data)
|
|
{
|
|
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
|
|
CPUClass *cc = CPU_CLASS(c);
|
|
DeviceClass *dc = DEVICE_CLASS(c);
|
|
|
|
device_class_set_parent_realize(dc, riscv_cpu_realize,
|
|
&mcc->parent_realize);
|
|
|
|
device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
|
|
|
|
cc->class_by_name = riscv_cpu_class_by_name;
|
|
cc->has_work = riscv_cpu_has_work;
|
|
cc->do_interrupt = riscv_cpu_do_interrupt;
|
|
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
|
|
cc->dump_state = riscv_cpu_dump_state;
|
|
cc->set_pc = riscv_cpu_set_pc;
|
|
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
|
|
cc->gdb_read_register = riscv_cpu_gdb_read_register;
|
|
cc->gdb_write_register = riscv_cpu_gdb_write_register;
|
|
cc->gdb_num_core_regs = 33;
|
|
#if defined(TARGET_RISCV32)
|
|
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
|
|
#elif defined(TARGET_RISCV64)
|
|
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
|
|
#endif
|
|
cc->gdb_stop_before_watchpoint = true;
|
|
cc->disas_set_info = riscv_cpu_disas_set_info;
|
|
#ifndef CONFIG_USER_ONLY
|
|
cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
|
|
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
|
|
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
|
|
#endif
|
|
#ifdef CONFIG_TCG
|
|
cc->tcg_initialize = riscv_translate_init;
|
|
cc->tlb_fill = riscv_cpu_tlb_fill;
|
|
#endif
|
|
/* For now, mark unmigratable: */
|
|
cc->vmsd = &vmstate_riscv_cpu;
|
|
device_class_set_props(dc, riscv_cpu_properties);
|
|
}
|
|
|
|
char *riscv_isa_string(RISCVCPU *cpu)
|
|
{
|
|
int i;
|
|
const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
|
|
char *isa_str = g_new(char, maxlen);
|
|
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
|
|
for (i = 0; i < sizeof(riscv_exts); i++) {
|
|
if (cpu->env.misa & RV(riscv_exts[i])) {
|
|
*p++ = qemu_tolower(riscv_exts[i]);
|
|
}
|
|
}
|
|
*p = '\0';
|
|
return isa_str;
|
|
}
|
|
|
|
static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
|
|
{
|
|
ObjectClass *class_a = (ObjectClass *)a;
|
|
ObjectClass *class_b = (ObjectClass *)b;
|
|
const char *name_a, *name_b;
|
|
|
|
name_a = object_class_get_name(class_a);
|
|
name_b = object_class_get_name(class_b);
|
|
return strcmp(name_a, name_b);
|
|
}
|
|
|
|
static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
|
|
{
|
|
const char *typename = object_class_get_name(OBJECT_CLASS(data));
|
|
int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
|
|
|
|
qemu_printf("%.*s\n", len, typename);
|
|
}
|
|
|
|
void riscv_cpu_list(void)
|
|
{
|
|
GSList *list;
|
|
|
|
list = object_class_get_list(TYPE_RISCV_CPU, false);
|
|
list = g_slist_sort(list, riscv_cpu_list_compare);
|
|
g_slist_foreach(list, riscv_cpu_list_entry, NULL);
|
|
g_slist_free(list);
|
|
}
|
|
|
|
#define DEFINE_CPU(type_name, initfn) \
|
|
{ \
|
|
.name = type_name, \
|
|
.parent = TYPE_RISCV_CPU, \
|
|
.instance_init = initfn \
|
|
}
|
|
|
|
static const TypeInfo riscv_cpu_type_infos[] = {
|
|
{
|
|
.name = TYPE_RISCV_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(RISCVCPU),
|
|
.instance_init = riscv_cpu_init,
|
|
.abstract = true,
|
|
.class_size = sizeof(RISCVCPUClass),
|
|
.class_init = riscv_cpu_class_init,
|
|
},
|
|
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
|
|
#if defined(TARGET_RISCV32)
|
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
|
|
#elif defined(TARGET_RISCV64)
|
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
|
|
#endif
|
|
};
|
|
|
|
DEFINE_TYPES(riscv_cpu_type_infos)
|