qemu/target
Daniel Henrique Barboza 8b3b345105 target/riscv/tcg: honor user choice for G MISA bits
RVG behaves like a profile: a single flag enables a set of bits. Right
now we're considering user choice when handling RVG and zicsr/zifencei
and ignoring user choice on MISA bits.

We'll add user warnings for profiles when the user disables its
mandatory extensions in the next patch. We'll do the same thing with RVG
now to keep consistency between RVG and profile handling.

First and foremost, create a new RVG only helper to avoid clogging
riscv_cpu_validate_set_extensions(). We do not want to annoy users with
RVG warnings like we did in the past (see 9b9741c38f), thus we'll only
warn if RVG was user set and the user disabled a RVG extension in the
command line.

For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then
becomes:

- if enabled, do nothing;
- if disabled and not user set, enable it;
- if disabled and user set, throw a warning that it's a RVG mandatory
  extension.

This same logic will be used for profiles in the next patch.

Note that this is a behavior change, where we would error out if the
user disabled either zicsr or zifencei. As long as users are explicitly
disabling things in the command line we'll let them have a go at it, at
least in this step. We'll error out later in the validation if needed.

Other notable changes from the previous RVG code:

- use riscv_cpu_write_misa_bit() instead of manually updating both
  env->misa_ext and env->misa_ext_mask;

- set zicsr and zifencei directly. We're already checking if they
  were user set and priv version will never fail for these
  extensions, making cpu_cfg_ext_auto_update() redundant.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10 18:47:47 +10:00
..
alpha target/alpha: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
arm Replace "iothread lock" with "BQL" in comments 2024-01-08 10:45:43 -05:00
avr target/avr: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
cris target/cris: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hexagon target/hexagon: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hppa system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
i386 qemu/main-loop: rename qemu_cond_wait_iothread() to qemu_cond_wait_bql() 2024-01-08 10:45:43 -05:00
loongarch system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
m68k target/m68k: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
microblaze target/microblaze: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
mips system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
nios2 target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
openrisc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
ppc qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD 2024-01-08 10:45:43 -05:00
riscv target/riscv/tcg: honor user choice for G MISA bits 2024-01-10 18:47:47 +10:00
rx target/rx: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
s390x system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
sh4 target/sh4: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
sparc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
tricore target/tricore: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
xtensa system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00