qemu/target/arm/tcg
Peter Maydell 442c9d682c target/arm: Convert ERET, ERETAA, ERETAB to decodetree
Convert the exception-return insns ERET, ERETA and ERETB to
decodetree. These were the last insns left in the legacy
decoder function disas_uncond_reg_b(), which allows us to
remove it.

The old decoder explicitly decoded the DRPS instruction,
only in order to call unallocated_encoding() on it, exactly
as would have happened if it hadn't decoded it. This is
because this insn always UNDEFs unless the CPU is in
halting-debug state, which we don't emulate. So we list
the pattern in a comment in a64.decode, but don't actively
decode it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org
2023-05-18 11:35:38 +01:00
..
a32-uncond.decode
a32.decode
a64.decode target/arm: Convert ERET, ERETAA, ERETAB to decodetree 2023-05-18 11:35:38 +01:00
arm_ldst.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
cpu32.c target/arm: move cpu_tcg to tcg/cpu32.c 2023-05-02 10:54:31 +01:00
cpu64.c target/arm: move cpu_tcg to tcg/cpu32.c 2023-05-02 10:54:31 +01:00
crypto_helper.c
helper-a64.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
helper-a64.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-mve.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-sme.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-sve.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
hflags.c target/arm: Move hflags code into the tcg directory 2023-02-27 13:27:04 +00:00
iwmmxt_helper.c
m-nocp.decode
m_helper.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
meson.build target/arm: Create decodetree skeleton for A64 2023-05-18 11:16:45 +01:00
mte_helper.c softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel 2023-03-28 15:24:06 -07:00
mve.decode
mve_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
neon_helper.c
op_helper.c
pauth_helper.c target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check 2023-05-12 16:01:25 +01:00
psci.c target/arm: Move psci.c into the tcg directory 2023-02-27 13:27:04 +00:00
sme-fa64.decode
sme.decode
sme_helper.c
sve.decode
sve_helper.c target/arm: Fix vd == vm overlap in sve_ldff1_z 2023-05-18 10:31:43 +01:00
sve_ldst_internal.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
t16.decode
t32.decode
tlb_helper.c target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 2023-04-20 10:21:16 +01:00
translate-a32.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
translate-a64.c target/arm: Convert ERET, ERETAA, ERETAB to decodetree 2023-05-18 11:35:38 +01:00
translate-a64.h target/arm: Drop new_tmp_a64_zero 2023-03-05 13:44:07 -08:00
translate-m-nocp.c target/arm: Drop tcg_temp_free from translator-m-nocp.c 2023-03-05 13:44:07 -08:00
translate-mve.c target/arm: Avoid tcg_const_* in translate-mve.c 2023-03-13 07:03:39 -07:00
translate-neon.c target/arm: Drop tcg_temp_free from translator-neon.c 2023-03-05 13:44:07 -08:00
translate-sme.c target/arm: Drop tcg_temp_free from translator-sme.c 2023-03-05 13:44:07 -08:00
translate-sve.c target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} 2023-03-13 07:03:39 -07:00
translate-vfp.c target/arm: Create gen_set_rmode, gen_restore_rmode 2023-03-13 06:44:38 -07:00
translate.c target/arm: Define and use new load_cpu_field_low32() 2023-05-02 15:47:41 +01:00
translate.h target/arm: Convert Add/subtract (immediate) to decodetree 2023-05-18 11:28:39 +01:00
vec_helper.c
vec_internal.h
vfp-uncond.decode
vfp.decode