Yu-Ming Chang 38c83e8d3a target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR ... Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies a register holding a zero value, an illegal instruction exception should be raised. Signed-off-by: Yu-Ming Chang <yumin686@andestech.com> Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <172100444279.18077.6893072378718059541-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-07-18 12:08:45 +10:00
..
insn_trans	target/riscv: Add amocas.[b|h] for Zabha	2024-07-18 12:00:42 +10:00
kvm	target/riscv/kvm: update KVM regs to Linux 6.10-rc5	2024-07-18 12:08:44 +10:00
tcg	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add cycle & instret privilege mode filtering support	2024-07-18 12:08:44 +10:00
cpu_cfg.h	target/riscv: Add cycle & instret privilege mode filtering properties	2024-07-18 12:08:44 +10:00
cpu_helper.c	target/riscv: Implement privilege mode filtering for cycle/instret	2024-07-18 12:08:44 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h	target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'	2024-04-26 15:31:37 +02:00
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	target/riscv: Expose the Smcntrpmf config	2024-07-18 12:08:45 +10:00
cpu.h	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
crypto_helper.c
csr.c	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
debug.c	target/riscv: Apply modularized matching conditions for icount trigger	2024-06-27 13:09:16 +10:00
debug.h	exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header	2024-04-26 17:03:05 +02:00
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()	2024-06-03 11:12:12 +10:00
helper.h	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
insn16.decode	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
insn32.decode	target/riscv: Add amocas.[b|h] for Zabha	2024-07-18 12:00:42 +10:00
instmap.h
internals.h	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
Kconfig	kconfig: express dependency of individual boards on libfdt	2024-05-10 15:45:15 +02:00
m128_helper.c
machine.c	target/riscv: Save counter values during countinhibit update	2024-07-18 12:08:44 +10:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c
op_helper.c	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
pmp.c	exec/cpu: Extract page-protection definitions to page-protection.h	2024-05-06 11:17:15 +02:00
pmp.h
pmu.c	target/riscv: Do not setup pmu timer if OF is disabled	2024-07-18 12:08:45 +10:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Move gen_cmpxchg before adding amocas.[b|h]	2024-07-18 12:00:42 +10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	exec/cpu: Extract page-protection definitions to page-protection.h	2024-05-06 11:17:15 +02:00
vector_internals.c	target/riscv: Fix the element agnostic function problem	2024-06-03 11:12:12 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c