a1559537d1
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_MMVEC_H
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#define HEXAGON_MMVEC_H
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#define MAX_VEC_SIZE_LOGBYTES 7
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#define MAX_VEC_SIZE_BYTES (1 << MAX_VEC_SIZE_LOGBYTES)
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#define NUM_VREGS 32
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#define NUM_QREGS 4
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typedef uint32_t VRegMask; /* at least NUM_VREGS bits */
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typedef uint32_t QRegMask; /* at least NUM_QREGS bits */
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#define VECTOR_SIZE_BYTE (fVECSIZE())
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typedef union {
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uint64_t ud[MAX_VEC_SIZE_BYTES / 8];
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int64_t d[MAX_VEC_SIZE_BYTES / 8];
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uint32_t uw[MAX_VEC_SIZE_BYTES / 4];
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int32_t w[MAX_VEC_SIZE_BYTES / 4];
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uint16_t uh[MAX_VEC_SIZE_BYTES / 2];
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int16_t h[MAX_VEC_SIZE_BYTES / 2];
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uint8_t ub[MAX_VEC_SIZE_BYTES / 1];
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int8_t b[MAX_VEC_SIZE_BYTES / 1];
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} MMVector;
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typedef union {
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uint64_t ud[2 * MAX_VEC_SIZE_BYTES / 8];
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int64_t d[2 * MAX_VEC_SIZE_BYTES / 8];
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uint32_t uw[2 * MAX_VEC_SIZE_BYTES / 4];
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int32_t w[2 * MAX_VEC_SIZE_BYTES / 4];
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uint16_t uh[2 * MAX_VEC_SIZE_BYTES / 2];
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int16_t h[2 * MAX_VEC_SIZE_BYTES / 2];
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uint8_t ub[2 * MAX_VEC_SIZE_BYTES / 1];
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int8_t b[2 * MAX_VEC_SIZE_BYTES / 1];
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MMVector v[2];
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} MMVectorPair;
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typedef union {
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uint64_t ud[MAX_VEC_SIZE_BYTES / 8 / 8];
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int64_t d[MAX_VEC_SIZE_BYTES / 8 / 8];
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uint32_t uw[MAX_VEC_SIZE_BYTES / 4 / 8];
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int32_t w[MAX_VEC_SIZE_BYTES / 4 / 8];
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uint16_t uh[MAX_VEC_SIZE_BYTES / 2 / 8];
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int16_t h[MAX_VEC_SIZE_BYTES / 2 / 8];
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uint8_t ub[MAX_VEC_SIZE_BYTES / 1 / 8];
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int8_t b[MAX_VEC_SIZE_BYTES / 1 / 8];
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} MMQReg;
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typedef struct {
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MMVector data;
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DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES);
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target_ulong va[MAX_VEC_SIZE_BYTES];
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bool op;
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int op_size;
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} VTCMStoreLog;
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/* Types of vector register assignment */
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typedef enum {
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EXT_DFL, /* Default */
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EXT_NEW, /* New - value used in the same packet */
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EXT_TMP /* Temp - value used but not stored to register */
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} VRegWriteType;
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#endif
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