774204cf98
This commit adds support for x2APIC transitions when writing to MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to TCG_EXT_FEATURES. The set_base in APICCommonClass now returns an integer to indicate error in execution. apic_set_base return -1 on invalid APIC state transition, accelerator can use this to raise appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
28 lines
859 B
C
28 lines
859 B
C
#ifndef APIC_H
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#define APIC_H
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/* apic.c */
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void apic_set_max_apic_id(uint32_t max_apic_id);
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int apic_accept_pic_intr(DeviceState *s);
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void apic_deliver_pic_intr(DeviceState *s, int level);
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void apic_deliver_nmi(DeviceState *d);
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int apic_get_interrupt(DeviceState *s);
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int cpu_set_apic_base(DeviceState *s, uint64_t val);
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uint64_t cpu_get_apic_base(DeviceState *s);
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void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(DeviceState *s);
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void apic_init_reset(DeviceState *s);
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void apic_sipi(DeviceState *s);
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void apic_poll_irq(DeviceState *d);
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void apic_designate_bsp(DeviceState *d, bool bsp);
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int apic_get_highest_priority_irr(DeviceState *dev);
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int apic_msr_read(int index, uint64_t *val);
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int apic_msr_write(int index, uint64_t val);
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bool is_x2apic_mode(DeviceState *d);
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/* pc.c */
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DeviceState *cpu_get_current_apic(void);
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#endif
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