qemu/target/mips
Yongbok Kim 59488dda1f target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16 19:18:45 +02:00
..
cp0_timer.c
cpu-qom.h
cpu.c
cpu.h
dsp_helper.c
gdbstub.c
helper.c
helper.h
internal.h
kvm_mips.h
kvm.c
lmi_helper.c
machine.c
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c
TODO
trace-events
translate_init.inc.c
translate.c target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 2018-08-16 19:18:45 +02:00