target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -4897,12 +4897,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *rn = "invalid";
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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switch (reg) {
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case 2:
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switch (sel) {
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case 0:
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
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rn = "EntryLo0";
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break;
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@ -4913,6 +4912,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case 3:
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switch (sel) {
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case 0:
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
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rn = "EntryLo1";
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break;
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@ -4965,12 +4965,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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const char *rn = "invalid";
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uint64_t mask = ctx->PAMask >> 36;
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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switch (reg) {
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case 2:
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switch (sel) {
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case 0:
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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tcg_gen_andi_tl(arg, arg, mask);
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gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
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rn = "EntryLo0";
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@ -4982,6 +4981,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case 3:
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switch (sel) {
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case 0:
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CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
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tcg_gen_andi_tl(arg, arg, mask);
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gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
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rn = "EntryLo1";
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