qemu/tests/tcg/i386/x86.csv

1	# x86 instruction set description version 0.2x	2018-05-08
2	# of the file	so a reader can skip past the comments and hand the
3	# 5. The validity of the instruction in 32-bit (aka compatibility	legacy) mode.
4	# distinguished only by operand size	like most arithmetic instructions.
5	# The instruction mnemonics are as used in the Intel manual	with a few exceptions.
6	# Perhaps most significantly	the argument syntaxes used in the mnemonic indicate
7	# exactly how to derive the argument from the instruction encoding	or vice versa.
8	# The encodings are also as used in the Intel manual	with automated corrections.
9	# For example	the manual lists many instruction forms using REX bytes
10	# to use the instruction. If multiple flags are required
11	# they are listed separated by plus signs	as in PCLMULQDQ+AVX.
12	# Instead	it is itself a comma-separated list of tags or hints derived by analysis
13	# If two address tags are listed	the instruction can be used with either of those
14	# If two operand tags are listed	the instruction can be used with either of those
15	# For instructions with different possible data sizes
16	# r/m encoding must specify a register or memory	respectively.
17	# Especially in newer instructions	the modrm constraint may be the only way
18	# instructions share the same encoding	except that the former requires the
19	# modrm byte's r/m to indicate a register	while the latter requires it to indicate memory.
20	# the manual lists an instruction twice	once with the optional 64-bit mode REX byte.
21	# Since most decoders will handle the REX byte separately	the form with the
22	# As an example	all instructions of SSE4a have such tag.
23	# bscale4 and bscale8 have the same meaning	but are used
24	# If instruction does not have bscaleX tag	it does not support EVEX broadcasting.

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