qemu/hw/riscv
Nathaniel Graff 40061ac0bc
sifive_uart: Implement interrupt pending register
The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.

Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20 12:08:43 -08:00
..
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
riscv_hart.c riscv_hart: Fix crash when introspecting the device 2018-07-19 09:05:48 -07:00
riscv_htif.c hw: Do not include "exec/address-spaces.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sifive_clint.c RISC-V: Fix CLINT timecmp low 32-bit writes 2018-12-20 12:08:43 -08:00
sifive_e.c RISC-V: Enable second UART on sifive_e and sifive_u 2018-12-20 12:08:43 -08:00
sifive_plic.c RISC-V: Fix PLIC pending bitfield reads 2018-12-20 12:08:43 -08:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c RISC-V: Enable second UART on sifive_e and sifive_u 2018-12-20 12:08:43 -08:00
sifive_uart.c sifive_uart: Implement interrupt pending register 2018-12-20 12:08:43 -08:00
spike.c riscv: spike: Fix memory leak in the board init 2018-11-08 08:41:06 -08:00
virt.c hw/riscv/virt: Connect the gpex PCIe 2018-12-20 11:45:20 -08:00