Sven Schnelle 6e5f530025 target/hppa: fix b,gate instruction ... b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31}); instead of saving the link address to register t. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-8-svens@stackframe.org> [rth: Move link check outside of ifndef CONFIG_USER_ONLY; use ctx->privilege; nullify the insn earlier.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2019-03-12 09:13:43 -07:00
..
cpu-qom.h	target-hppa: Add framework and enable compilation	2017-01-23 09:52:40 -08:00
cpu.c	fpu/softfloat: Specialize on snan_bit_is_one	2018-05-17 15:27:15 -07:00
cpu.h	target/hppa: Include priv level in user-only iaoq	2018-03-26 22:56:57 +08:00
gdbstub.c	target/hppa: fix setting registers via gdb	2019-02-06 10:49:21 +00:00
helper.c	target: Do not include "exec/exec-all.h" if it is not necessary	2018-06-01 14:15:10 +02:00
helper.h	target/hppa: Implement PROBE for system mode	2018-01-31 05:30:50 -08:00
insns.decode	target/hppa: ignore DIAG opcode	2019-03-12 09:13:43 -07:00
int_helper.c	target: Do not include "exec/exec-all.h" if it is not necessary	2018-06-01 14:15:10 +02:00
machine.c	vmstate: constify VMStateField	2018-11-27 15:35:15 +01:00
Makefile.objs	target/hppa: Begin using scripts/decodetree.py	2019-02-12 08:48:27 -08:00
mem_helper.c	target/hppa: add TLB trace events	2019-03-12 09:13:43 -07:00
op_helper.c	target/hppa: remove PSW I/R/Q bit check	2019-03-12 09:13:43 -07:00
trace-events	target/hppa: add TLB trace events	2019-03-12 09:13:43 -07:00
translate.c	target/hppa: fix b,gate instruction	2019-03-12 09:13:43 -07:00