Richard Henderson 6cafec92f1 target/riscv: Merge argument decode for RVC shifti ... Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-24 12:09:22 -07:00
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trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-24 12:09:22 -07:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-13 10:34:06 +01:00
trans_rvc.inc.c	target/riscv: Merge argument decode for RVC shifti	2019-05-24 12:09:22 -07:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-13 10:34:06 +01:00
trans_rvi.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-24 12:09:22 -07:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-22 00:26:39 -07:00