Richard Henderson 6cafec92f1 target/riscv: Merge argument decode for RVC shifti ... Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-24 12:09:22 -07:00
..
insn_trans	target/riscv: Merge argument decode for RVC shifti	2019-05-24 12:09:22 -07:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 05:13:24 -07:00
cpu_helper.c	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-10 11:12:50 -07:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
cpu.c	target/riscv: Convert to CPUClass::tlb_fill	2019-05-10 11:12:50 -07:00
cpu.h	target/riscv: Convert to CPUClass::tlb_fill	2019-05-10 11:12:50 -07:00
csr.c	RISC-V: Add support for vectored interrupts	2019-03-19 05:14:39 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
helper.h
insn16.decode	target/riscv: Merge argument decode for RVC shifti	2019-05-24 12:09:22 -07:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-24 12:09:22 -07:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	target/riscv: Use --static-decode for decodetree	2019-05-24 12:09:22 -07:00
op_helper.c	target/riscv: Do not allow sfence.vma from user mode	2019-05-24 12:09:19 -07:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 05:14:38 -07:00
pmp.h	Clean up ill-advised or unusual header guards	2019-05-13 08:58:55 +02:00
trace-events	RISC-V: Convert trap debugging to trace events	2019-03-19 05:14:40 -07:00
translate.c	target/riscv: Merge argument decode for RVC shifti	2019-05-24 12:09:22 -07:00