6864fa3897
This patch updates the sun4u model to being much closer to a real Ultra 5 by moving devices behind the 2 simba PCI bridges (A and B) as found on real hardware. The most noticeable change introduced by this patchset is that in-built devices are no longer attached to the PCI root bus, but instead behind PCI bridge A. Along with this the interrupt routing is updated accordingly to match the official documentation. Since the existing code currently bypasses the PCI bridge interrupt swizzling, the interrupt mapping functions are reorganised so that pci_pbm_map_irq() is used by the PCI bridges and pci_apb_map_irq() is used by the PCI host bridge. Behind the sabre PCI host bridge, the PCI IO space now needs to be split into two separate halves at 0x8000000. Therefore we also setup a new PCI IO space region of increased size on the PCI host bridge and enable 32-bit PCI IO accesses to allow IO accesses to reach devices behind PCI bridge B correctly. As part of this change we also combine the onboard sunhme NIC and the ebus into a single multi-function device as done on a real Ultra 5. For other NICs the existing behaviour is preserved, i.e. we initialise them and place them into the next free slot on PCI bus B. Finally we mark the physically unavailable slots (plus slot 0 in busA) as reserved to ensure that users can't plug devices into non-existent slots which will break interrupt routing. Note: since this commit changes PCI topology and interrupt routing, an updated openbios-sparc64 binary is included with this commit containing the associated changes to maintain bisectability. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> |
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| .. | ||
| apb.c | ||
| bonito.c | ||
| gpex.c | ||
| grackle.c | ||
| Makefile.objs | ||
| pam.c | ||
| piix.c | ||
| ppce500.c | ||
| prep.c | ||
| q35.c | ||
| uninorth.c | ||
| versatile.c | ||
| xilinx-pcie.c | ||