pci: Add INTERFACE_PCIE_DEVICE to all PCIe devices
Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE. Cc: Keith Busch <keith.busch@intel.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Cc: Dmitry Fleytman <dmitry@daynix.com> Cc: Jason Wang <jasowang@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Hannes Reinecke <hare@suse.com> Cc: qemu-block@nongnu.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {
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.instance_size = sizeof(NvmeCtrl),
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.class_init = nvme_class_init,
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.instance_init = nvme_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void nvme_register_types(void)
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@ -710,6 +710,10 @@ static const TypeInfo e1000e_info = {
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.instance_size = sizeof(E1000EState),
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.class_init = e1000e_class_init,
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.instance_init = e1000e_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void e1000e_register_types(void)
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@ -192,6 +192,7 @@ static const TypeInfo pcie_pci_bridge_info = {
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.class_init = pcie_pci_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_HOTPLUG_HANDLER },
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{ INTERFACE_PCIE_DEVICE },
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{ },
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}
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};
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@ -161,6 +161,10 @@ static const TypeInfo rp_info = {
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.class_init = rp_class_init,
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.abstract = true,
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.class_size = sizeof(PCIERootPortClass),
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void rp_register_types(void)
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@ -196,6 +196,10 @@ static const TypeInfo xio3130_downstream_info = {
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.name = "xio3130-downstream",
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.parent = TYPE_PCIE_SLOT,
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.class_init = xio3130_downstream_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void xio3130_downstream_register_types(void)
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@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {
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.name = "x3130-upstream",
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.parent = TYPE_PCIE_PORT,
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.class_init = xio3130_upstream_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void xio3130_upstream_register_types(void)
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@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {
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.parent = TYPE_PCI_BRIDGE,
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.instance_size = sizeof(XilinxPCIERoot),
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.class_init = xilinx_pcie_root_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void xilinx_pcie_register(void)
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@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {
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int osts;
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const VMStateDescription *vmsd;
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Property *props;
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InterfaceInfo *interfaces;
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} MegasasInfo;
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static struct MegasasInfo megasas_devices[] = {
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@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {
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.is_express = true,
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.vmsd = &vmstate_megasas_gen2,
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.props = megasas_properties_gen2,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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}
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};
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@ -2531,6 +2536,7 @@ static void megasas_register_types(void)
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type_info.parent = TYPE_MEGASAS_BASE;
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type_info.class_data = (void *)info;
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type_info.class_init = megasas_class_init;
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type_info.interfaces = info->interfaces;
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type_register(&type_info);
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}
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