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qemu/include/hw/riscv
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Alistair Francis 8486eb8cdc hw/riscv: microchip_pfsoc: Use the PLIC config helper function 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com
2021-10-28 14:39:23 +10:00
..
boot_opensbi.h
…
boot.h
hw/riscv: boot: Add a PLIC config string function
2021-10-28 14:39:23 +10:00
microchip_pfsoc.h
hw/riscv: microchip_pfsoc: Use the PLIC config helper function
2021-10-28 14:39:23 +10:00
numa.h
…
opentitan.h
hw/riscv: opentitan: Update to the latest build
2021-10-22 23:35:47 +10:00
riscv_hart.h
…
shakti_c.h
hw/riscv: Connect Shakti UART to Shakti platform
2021-05-11 20:02:06 +10:00
sifive_cpu.h
…
sifive_e.h
…
sifive_u.h
hw/riscv: sifive_u: Use the PLIC config helper function
2021-10-28 14:39:23 +10:00
spike.h
riscv: spike: Remove target macro conditionals
2020-12-17 21:56:44 -08:00
virt.h
hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-10-28 14:39:23 +10:00