Alex Bennée d54c6d3b5d tests/tcg: add memory-sve test for aarch64 ...

This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Robert Henry <robhenry@microsoft.com>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
Message-Id: <20230124180127.1881110-26-alex.bennee@linaro.org>

2023-02-02 11:48:20 +00:00

..

gdbstub

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system

tests/tcg: add memory-sve test for aarch64

2023-02-02 11:48:20 +00:00

bti-1.c

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bti-2.c

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bti-3.c

target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user

2022-05-05 09:35:50 +01:00

bti-crt.inc.c

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fcvt.ref

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float_convd.ref

tests/tcg: add float_convd test

2022-04-20 16:04:20 +01:00

float_convs.ref

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float_madds.ref

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Makefile.softmmu-target

tests/tcg: add memory-sve test for aarch64

2023-02-02 11:48:20 +00:00

Makefile.target

target/arm: align exposed ID registers with Linux

2023-01-05 14:12:34 +00:00

mte-1.c

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mte-2.c

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mte-3.c

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mte-4.c

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mte-5.c

test/tcg/aarch64: Add mte-5

2021-04-30 11:16:49 +01:00

mte-6.c

accel/tcg: Preserve PAGE_ANON when changing page permissions

2021-04-12 11:06:24 +01:00

mte-7.c

target/arm: Fix mte page crossing test

2021-06-16 14:33:51 +01:00

mte.h

accel/tcg: Preserve PAGE_ANON when changing page permissions

2021-04-12 11:06:24 +01:00

pauth-1.c

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pauth-2.c

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pauth-4.c

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pauth-5.c

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pcalign-a64.c

tests/tcg: Add arm and aarch64 pc alignment tests

2021-12-15 10:35:26 +00:00

semicall.h

semihosting: move semihosting tests to multiarch

2021-03-24 14:25:03 +00:00

sve-ioctls.c

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sysregs.c

target/arm: align exposed ID registers with Linux

2023-01-05 14:12:34 +00:00

test-826.c

target/arm: Fix sve2 ldnt1 and stnt1

2022-03-18 10:55:15 +00:00