test/tcg/aarch64: Add mte-5
Buglink: https://bugs.launchpad.net/bugs/1921948 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -37,7 +37,7 @@ AARCH64_TESTS += bti-2
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# MTE Tests
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ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
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AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6
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AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6
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mte-%: CFLAGS += -march=armv8.5-a+memtag
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endif
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44
tests/tcg/aarch64/mte-5.c
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44
tests/tcg/aarch64/mte-5.c
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@ -0,0 +1,44 @@
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/*
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* Memory tagging, faulting unaligned access.
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*
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* Copyright (c) 2021 Linaro Ltd
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "mte.h"
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void pass(int sig, siginfo_t *info, void *uc)
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{
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assert(info->si_code == SEGV_MTESERR);
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exit(0);
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}
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int main(int ac, char **av)
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{
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struct sigaction sa;
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void *p0, *p1, *p2;
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long excl = 1;
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enable_mte(PR_MTE_TCF_SYNC);
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p0 = alloc_mte_mem(sizeof(*p0));
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/* Create two differently tagged pointers. */
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asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
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asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
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assert(excl != 1);
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asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
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assert(p1 != p2);
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memset(&sa, 0, sizeof(sa));
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sa.sa_sigaction = pass;
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sa.sa_flags = SA_SIGINFO;
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sigaction(SIGSEGV, &sa, NULL);
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/* Store store two different tags in sequential granules. */
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asm("stg %0, [%0]" : : "r"(p1));
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asm("stg %0, [%0]" : : "r"(p2 + 16));
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/* Perform an unaligned load crossing the granules. */
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asm volatile("ldr %0, [%1]" : "=r"(p0) : "r"(p1 + 12));
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abort();
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}
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