Jonathan Cameron 314f5033c6 hw/pci-bridge/cxl_downstream: Set default link width and link speed ...

Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

2023-11-07 03:39:11 -05:00

..

cxl_downstream.c

hw/pci-bridge/cxl_downstream: Set default link width and link speed

2023-11-07 03:39:11 -05:00

cxl_root_port.c

hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt

2023-11-07 03:39:11 -05:00

cxl_upstream.c

hw/pci-bridge/cxl_upstream: Move defintion of device to header.

2023-11-07 03:39:11 -05:00

gen_pcie_root_port.c

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i82801b11.c

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ioh3420.c

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Kconfig

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meson.build

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pci_bridge_dev.c

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pci_expander_bridge_stubs.c

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pci_expander_bridge.c

hw/pci: spelling fixes

2023-09-20 07:54:34 +03:00

pcie_pci_bridge.c

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pcie_root_port.c

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simba.c

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xio3130_downstream.c

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xio3130_upstream.c

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