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hw/pci: spelling fixes

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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:27:04 +03:00
parent 2431f4f184
commit f1c0cff8a2
13 changed files with 17 additions and 17 deletions
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2
hw/pci-bridge/cxl_downstream.c
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@ -42,7 +42,7 @@ static void latch_registers(CXLDownstreamPort *dsp)
CXL2_DOWNSTREAM_PORT);
}
/* TODO: Look at sharing this code acorss all CXL port types */
/* TODO: Look at sharing this code across all CXL port types */
static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
uint32_t val, int len)
{

2
hw/pci-bridge/pci_expander_bridge.c
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@ -263,7 +263,7 @@ static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
/*
* First carry out normal swizzle to handle
* multple root ports on a pxb instance.
* multiple root ports on a pxb instance.
*/
pin = pci_swizzle_map_irq_fn(pci_dev, pin);

2
hw/pci-host/bonito.c
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@ -62,7 +62,7 @@
#define DPRINTF(fmt, ...)
#endif
/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
/* from linux source code. include/asm-mips/mips-boards/bonito64.h*/
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)

4
hw/pci-host/designware.c
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@ -488,7 +488,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
/*
* If no inbound iATU windows are configured, HW defaults to
* letting inbound TLPs to pass in. We emulate that by exlicitly
* letting inbound TLPs to pass in. We emulate that by explicitly
* configuring first inbound window to cover all of target's
* address space.
*
@ -503,7 +503,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
&designware_pci_host_msi_ops,
root, "pcie-msi", 0x4);
/*
* We initially place MSI interrupt I/O region a adress 0 and
* We initially place MSI interrupt I/O region at address 0 and
* disable it. It'll be later moved to correct offset and enabled
* in designware_pcie_root_update_msi_mapping() as a part of
* initialization done by guest OS

2
hw/pci-host/dino.c
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@ -1,5 +1,5 @@
/*
* HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
* HP-PARISC Dino PCI chipset emulation, as in B160L and similar machines
*
* (C) 2017-2019 by Helge Deller <deller@gmx.de>
*

2
hw/pci-host/gpex-acpi.c
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@ -177,7 +177,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
acpi_dsdt_add_pci_route_table(dev, cfg->irq);
/*
* Resources defined for PXBs are composed by the folling parts:
* Resources defined for PXBs are composed of the following parts:
* 1. The resources the pci-brige/pcie-root-port need.
* 2. The resources the devices behind pxb need.
*/

4
hw/pci-host/gt64120.c
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@ -331,9 +331,9 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
/*
* The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
* Command Register determines how data transactions from the CPU to/from
* PCI are handled along with the setting of the Endianess bit in the CPU
* PCI are handled along with the setting of the Endianness bit in the CPU
* Configuration Register. See:
* - Table 16: 32-bit PCI Transaction Endianess
* - Table 16: 32-bit PCI Transaction Endianness
* - Table 158: PCI_0 Command, Offset: 0xc00
*/

2
hw/pci-host/pnv_phb.c
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@ -25,7 +25,7 @@
* state associated with the child has an id, use it as QOM id.
* Otherwise use object_typename[index] as QOM id.
*
* This helper does both operations at the same time because seting
* This helper does both operations at the same time because setting
* a new QOM child will erase the bus parent of the device. This happens
* because object_unparent() will call object_property_del_child(),
* which in turn calls the property release callback prop->release if

2
hw/pci-host/pnv_phb3.c
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@ -757,7 +757,7 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr,
* We only support non-translate in top window.
*
* TODO: Venice/Murano support it on bottom window above 4G and
* Naples suports it on everything
* Naples supports it on everything
*/
if (!(tve & PPC_BIT(51))) {
phb3_error(phb, "xlate for invalid non-translate TVE");

2
hw/pci-host/pnv_phb3_msi.c
View File

@ -281,7 +281,7 @@ static void phb3_msi_instance_init(Object *obj)
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
/* Will be overriden later */
/* Will be overridden later */
ics->offset = 0;
}

6
hw/pci-host/pnv_phb4.c
View File

@ -207,7 +207,7 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]);
}
/* TODO: Figure out how to implemet/decode AOMASK */
/* TODO: Figure out how to implement/decode AOMASK */
/* Check if it matches an enabled MMIO region in the PEC stack */
if (memory_region_is_mapped(&phb->mmbar0) &&
@ -391,7 +391,7 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val)
case IODA3_TBL_MBT:
*tptr = val;
/* Copy accross the valid bit to the other half */
/* Copy across the valid bit to the other half */
phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull;
phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val;
@ -1408,7 +1408,7 @@ static void pnv_phb4_msi_write(void *opaque, hwaddr addr,
return;
}
/* TODO: check PE/MSI assignement */
/* TODO: check PE/MSI assignment */
qemu_irq_pulse(phb->qirqs[src]);
}

2
hw/pci/pcie_aer.c
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@ -324,7 +324,7 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
* it isn't implemented in qemu right now.
* So just discard the error for now.
* OS which cares of aer would receive errors via
* native aer mechanims, so this wouldn't matter.
* native aer mechanisms, so this wouldn't matter.
*/
}

2
hw/pci/shpc.c
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@ -615,7 +615,7 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar,
}
if (nslots > SHPC_MAX_SLOTS ||
SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
/* TODO: report an error mesage that makes sense. */
/* TODO: report an error message that makes sense. */
return -EINVAL;
}
shpc->nslots = nslots;