qemu/target
Peter Maydell 5bdd374347 * Migrate MSR_SMI_COUNT (Liran)
* Update kernel headers (Gerd, myself)
 * SEV support (Brijesh)
 
 I have not tested non-x86 compilation, but I reordered the SEV patches
 so that all non-x86-specific changes go first to catch any possible
 issues (which weren't there anyway :)).
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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-sev' into staging

* Migrate MSR_SMI_COUNT (Liran)
* Update kernel headers (Gerd, myself)
* SEV support (Brijesh)

I have not tested non-x86 compilation, but I reordered the SEV patches
so that all non-x86-specific changes go first to catch any possible
issues (which weren't there anyway :)).

# gpg: Signature made Tue 13 Mar 2018 16:37:06 GMT
# gpg:                using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream-sev: (22 commits)
  sev/i386: add sev_get_capabilities()
  sev/i386: qmp: add query-sev-capabilities command
  sev/i386: qmp: add query-sev-launch-measure command
  sev/i386: hmp: add 'info sev' command
  cpu/i386: populate CPUID 0x8000_001F when SEV is active
  sev/i386: add migration blocker
  sev/i386: finalize the SEV guest launch flow
  sev/i386: add support to LAUNCH_MEASURE command
  target/i386: encrypt bios rom
  sev/i386: add command to encrypt guest memory region
  sev/i386: add command to create launch memory encryption context
  sev/i386: register the guest memory range which may contain encrypted data
  sev/i386: add command to initialize the memory encryption context
  include: add psp-sev.h header file
  sev/i386: qmp: add query-sev command
  target/i386: add Secure Encrypted Virtualization (SEV) object
  kvm: introduce memory encryption APIs
  kvm: add memory encryption context
  docs: add AMD Secure Encrypted Virtualization (SEV)
  machine: add memory-encryption option
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-15 16:49:30 +00:00
..
alpha target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
arm target/arm: Make 'any' CPU just an alias for 'max' 2018-03-09 17:09:44 +00:00
cris qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
hppa target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
i386 * Migrate MSR_SMI_COUNT (Liran) 2018-03-15 16:49:30 +00:00
lm32 qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
m68k target/m68k: implement fcosh 2018-03-13 16:35:05 +01:00
microblaze target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
mips qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
moxie target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
nios2 target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
openrisc target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
ppc PowerPC: Add TS bits into msr_mask 2018-03-06 13:16:29 +11:00
riscv RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
s390x target/s390x: Remove leading underscores from #defines 2018-03-08 15:49:23 +01:00
sh4 target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
sparc sparc: fix leon3 casa instruction when MMU is disabled 2018-03-08 07:22:03 +00:00
tilegx qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
tricore tricore: renamed masking of PIE 2018-03-02 11:46:36 +01:00
unicore32 ui/curses: build as module 2018-03-05 08:44:11 +01:00
xtensa target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00