Alistair Francis d31e970a01 riscv/opentitan: Update the OpenTitan memory layout ...

OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com

2020-12-17 21:56:44 -08:00

..

boot.c

hw/riscv: Use the CPU to determine if 32-bit

2020-12-17 21:56:44 -08:00

Kconfig

hw/riscv: microchip_pfsoc: Connect the SYSREG module

2020-11-03 07:17:23 -08:00

meson.build

hw/riscv: Always build riscv_hart.c

2020-09-09 15:54:19 -07:00

microchip_pfsoc.c

hw/riscv: microchip_pfsoc: add QSPI NOR flash

2020-12-17 21:56:43 -08:00

numa.c

hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

2020-08-25 09:11:35 -07:00

opentitan.c

riscv/opentitan: Update the OpenTitan memory layout

2020-12-17 21:56:44 -08:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

sifive_e.c

hw/riscv: Load the kernel after the firmware

2020-10-22 12:00:22 -07:00

sifive_u.c

hw/riscv: Use the CPU to determine if 32-bit

2020-12-17 21:56:44 -08:00

spike.c

hw/riscv: Use the CPU to determine if 32-bit

2020-12-17 21:56:44 -08:00

virt.c

hw/riscv: Use the CPU to determine if 32-bit

2020-12-17 21:56:44 -08:00