qemu/hw/riscv
Bin Meng 56f6e31e7b hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.

For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
The following perepherals are created as an unimplemented device:

- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG

More devices will be added later.

The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services

To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit

The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09 15:54:18 -07:00
..
boot.c RISC-V: Support 64 bit start address 2020-07-13 17:25:37 -07:00
Kconfig hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board 2020-09-09 15:54:18 -07:00
meson.build hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board 2020-09-09 15:54:18 -07:00
microchip_pfsoc.c hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board 2020-09-09 15:54:18 -07:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c hw/riscv: Allow creating multiple instances of CLINT 2020-08-25 09:11:35 -07:00
sifive_e_prci.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_e.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
sifive_gpio.c hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 2020-06-19 08:25:27 -07:00
sifive_plic.c hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_test.c riscv: sifive_test: Allow 16-bit writes to memory region 2020-09-09 15:54:18 -07:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c
sifive_u.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
trace-events
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
virt.c hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00