79e73b5df0
clang version 18.1.6 assumes a register is 64-bit by default and complains if a 32-bit value is given. Explicitly specify register width when passing a 32-bit value. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240627-tcg-v2-3-1690a813348e@daynix.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-5-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-10-alex.bennee@linaro.org>
43 lines
957 B
C
43 lines
957 B
C
/*
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* BTI vs PACIASP
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*/
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#include "bti-crt.c.inc"
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static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
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{
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uc->uc_mcontext.pc += 8;
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uc->uc_mcontext.pstate = 1;
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}
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#define BTYPE_1() \
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asm("mov %w0,#1; adr x16, 1f; br x16; 1: hint #25; mov %w0,#0" \
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: "=r"(skipped) : : "x16", "x30")
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#define BTYPE_2() \
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asm("mov %w0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %w0,#0" \
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: "=r"(skipped) : : "x16", "x30")
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#define BTYPE_3() \
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asm("mov %w0,#1; adr x15, 1f; br x15; 1: hint #25; mov %w0,#0" \
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: "=r"(skipped) : : "x15", "x30")
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#define TEST(WHICH, EXPECT) \
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do { WHICH(); fail += skipped ^ EXPECT; } while (0)
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int main()
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{
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int fail = 0;
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int skipped;
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/* Signal-like with SA_SIGINFO. */
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signal_info(SIGILL, skip2_sigill);
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/* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
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TEST(BTYPE_1, 0);
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TEST(BTYPE_2, 0);
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TEST(BTYPE_3, 1);
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return fail;
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}
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