55c57023b7
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out. The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode. This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations. The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller). Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
369 lines
13 KiB
C
369 lines
13 KiB
C
/*
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* ASPEED Ast10x0 SoC
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*
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* Copyright (C) 2022 ASPEED Technology Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* Implementation extracted from the AST2600 and adapted for Ast10x0.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/qdev-clock.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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static const hwaddr aspeed_soc_ast1030_memmap[] = {
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[ASPEED_DEV_SRAM] = 0x00000000,
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[ASPEED_DEV_SBC] = 0x79000000,
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[ASPEED_DEV_IOMEM] = 0x7E600000,
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[ASPEED_DEV_PWM] = 0x7E610000,
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[ASPEED_DEV_FMC] = 0x7E620000,
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[ASPEED_DEV_SPI1] = 0x7E630000,
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[ASPEED_DEV_SPI2] = 0x7E640000,
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[ASPEED_DEV_SCU] = 0x7E6E2000,
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[ASPEED_DEV_ADC] = 0x7E6E9000,
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[ASPEED_DEV_SBC] = 0x7E6F2000,
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[ASPEED_DEV_GPIO] = 0x7E780000,
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[ASPEED_DEV_TIMER1] = 0x7E782000,
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[ASPEED_DEV_UART1] = 0x7E783000,
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[ASPEED_DEV_UART2] = 0x7E78D000,
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[ASPEED_DEV_UART3] = 0x7E78E000,
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[ASPEED_DEV_UART4] = 0x7E78F000,
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[ASPEED_DEV_UART5] = 0x7E784000,
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[ASPEED_DEV_UART6] = 0x7E790000,
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[ASPEED_DEV_UART7] = 0x7E790100,
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[ASPEED_DEV_UART8] = 0x7E790200,
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[ASPEED_DEV_UART9] = 0x7E790300,
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[ASPEED_DEV_UART10] = 0x7E790400,
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[ASPEED_DEV_UART11] = 0x7E790500,
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[ASPEED_DEV_UART12] = 0x7E790600,
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[ASPEED_DEV_UART13] = 0x7E790700,
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[ASPEED_DEV_WDT] = 0x7E785000,
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[ASPEED_DEV_LPC] = 0x7E789000,
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[ASPEED_DEV_PECI] = 0x7E78B000,
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[ASPEED_DEV_I2C] = 0x7E7B0000,
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};
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static const int aspeed_soc_ast1030_irqmap[] = {
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[ASPEED_DEV_UART1] = 47,
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[ASPEED_DEV_UART2] = 48,
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[ASPEED_DEV_UART3] = 49,
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[ASPEED_DEV_UART4] = 50,
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[ASPEED_DEV_UART5] = 8,
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[ASPEED_DEV_UART6] = 57,
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[ASPEED_DEV_UART7] = 58,
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[ASPEED_DEV_UART8] = 59,
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[ASPEED_DEV_UART9] = 60,
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[ASPEED_DEV_UART10] = 61,
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[ASPEED_DEV_UART11] = 62,
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[ASPEED_DEV_UART12] = 63,
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[ASPEED_DEV_UART13] = 64,
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[ASPEED_DEV_GPIO] = 11,
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[ASPEED_DEV_TIMER1] = 16,
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[ASPEED_DEV_TIMER2] = 17,
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[ASPEED_DEV_TIMER3] = 18,
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[ASPEED_DEV_TIMER4] = 19,
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[ASPEED_DEV_TIMER5] = 20,
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[ASPEED_DEV_TIMER6] = 21,
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[ASPEED_DEV_TIMER7] = 22,
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[ASPEED_DEV_TIMER8] = 23,
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[ASPEED_DEV_WDT] = 24,
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[ASPEED_DEV_LPC] = 35,
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[ASPEED_DEV_PECI] = 38,
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[ASPEED_DEV_FMC] = 39,
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[ASPEED_DEV_PWM] = 44,
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[ASPEED_DEV_ADC] = 46,
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[ASPEED_DEV_SPI1] = 65,
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[ASPEED_DEV_SPI2] = 66,
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[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
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[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
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};
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static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
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}
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static void aspeed_soc_ast1030_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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char socname[8];
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char typename[64];
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int i;
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
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s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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object_initialize_child(obj, "scu", &s->scu, typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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object_initialize_child(obj, "i2c", &s->i2c, typename);
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
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snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
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object_initialize_child(obj, "adc", &s->adc, typename);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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object_initialize_child(obj, "fmc", &s->fmc, typename);
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
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}
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object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
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object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
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object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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object_initialize_child(obj, "gpio", &s->gpio, typename);
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object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
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TYPE_UNIMPLEMENTED_DEVICE);
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}
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static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
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{
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AspeedSoCState *s = ASPEED_SOC(dev_soc);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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DeviceState *armv7m;
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Error *err = NULL;
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int i;
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if (!clock_has_source(s->sysclk)) {
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error_setg(errp, "sysclk clock must be wired up by the board code");
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return;
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}
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/* General I/O memory space to catch all unimplemented device */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
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sc->memmap[ASPEED_DEV_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
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"aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
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0x40000);
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/* AST1030 CPU Core */
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 256);
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qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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object_property_set_link(OBJECT(&s->armv7m), "memory",
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OBJECT(s->memory), &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
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/* Internal SRAM */
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memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SRAM],
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&s->sram);
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/* SCU */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
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for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_I2C] + i);
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/* The AST1030 I2C controller has one IRQ per bus. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
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}
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/* PECI */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
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sc->memmap[ASPEED_DEV_PECI]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
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/* LPC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
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/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
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/*
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* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
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*/
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
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/* UART */
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aspeed_soc_uart_init(s);
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/* Timer */
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object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
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sc->memmap[ASPEED_DEV_TIMER1]);
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* ADC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
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/* FMC, The number of CS is set at the board level */
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object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
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ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
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/* SPI */
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for (i = 0; i < sc->spis_num; i++) {
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object_property_set_link(OBJECT(&s->spi[i]), "dram",
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OBJECT(&s->sram), &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
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sc->memmap[ASPEED_DEV_SPI1 + i]);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
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ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
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}
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/* Secure Boot Controller */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
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/* Watch dog */
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for (i = 0; i < sc->wdts_num; i++) {
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AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
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object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
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sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
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}
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/* GPIO */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
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sc->memmap[ASPEED_DEV_GPIO]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
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}
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static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
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dc->realize = aspeed_soc_ast1030_realize;
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sc->name = "ast1030-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
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sc->silicon_rev = AST1030_A1_SILICON_REV;
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sc->sram_size = 0xc0000;
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sc->spis_num = 2;
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sc->ehcis_num = 0;
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sc->wdts_num = 4;
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sc->macs_num = 1;
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sc->uarts_num = 13;
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sc->irqmap = aspeed_soc_ast1030_irqmap;
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sc->memmap = aspeed_soc_ast1030_memmap;
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sc->num_cpus = 1;
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sc->get_irq = aspeed_soc_ast1030_get_irq;
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}
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static const TypeInfo aspeed_soc_ast1030_type_info = {
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.name = "ast1030-a1",
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.parent = TYPE_ASPEED_SOC,
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.instance_size = sizeof(AspeedSoCState),
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.instance_init = aspeed_soc_ast1030_init,
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.class_init = aspeed_soc_ast1030_class_init,
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.class_size = sizeof(AspeedSoCClass),
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};
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static void aspeed_soc_register_types(void)
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{
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type_register_static(&aspeed_soc_ast1030_type_info);
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}
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type_init(aspeed_soc_register_types)
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