b254c342cf
Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers. Mechanical change using the following Coccinelle spatch script: @@ expression cpu; expression flags; @@ - cpu->tcg_cflags & flags + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - (tcg_cflags_has(cpu, flags)) + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - cpu->tcg_cflags |= flags; + tcg_cflags_set(cpu, flags); Then manually moving the declarations, and adding both tcg_cflags_has() and tcg_cflags_set() definitions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-15-philmd@linaro.org>
226 lines
6.2 KiB
C
226 lines
6.2 KiB
C
/*
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* TriCore emulation for qemu: main translation routines.
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*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/error-report.h"
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#include "tcg/debug-assert.h"
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static inline void set_feature(CPUTriCoreState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static const gchar *tricore_gdb_arch_name(CPUState *cs)
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{
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return "tricore";
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}
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static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
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{
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cpu_env(cs)->PC = value & ~(target_ulong)1;
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}
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static vaddr tricore_cpu_get_pc(CPUState *cs)
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{
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return cpu_env(cs)->PC;
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}
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static void tricore_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
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cpu_env(cs)->PC = tb->pc;
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}
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static void tricore_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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cpu_env(cs)->PC = data[0];
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}
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static void tricore_cpu_reset_hold(Object *obj, ResetType type)
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{
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CPUState *cs = CPU(obj);
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TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
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if (tcc->parent_phases.hold) {
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tcc->parent_phases.hold(obj, type);
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}
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cpu_state_reset(cpu_env(cs));
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}
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static bool tricore_cpu_has_work(CPUState *cs)
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{
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return true;
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}
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static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
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{
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return 0;
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}
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static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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TriCoreCPU *cpu = TRICORE_CPU(dev);
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TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
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CPUTriCoreState *env = &cpu->env;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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/* Some features automatically imply others */
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if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
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set_feature(env, TRICORE_FEATURE_161);
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}
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if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
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set_feature(env, TRICORE_FEATURE_16);
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}
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if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
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set_feature(env, TRICORE_FEATURE_131);
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}
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if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
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set_feature(env, TRICORE_FEATURE_13);
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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tcc->parent_realize(dev, errp);
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}
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static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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return oc;
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}
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static void tc1796_initfn(Object *obj)
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{
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TriCoreCPU *cpu = TRICORE_CPU(obj);
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set_feature(&cpu->env, TRICORE_FEATURE_13);
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}
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static void tc1797_initfn(Object *obj)
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{
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TriCoreCPU *cpu = TRICORE_CPU(obj);
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set_feature(&cpu->env, TRICORE_FEATURE_131);
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}
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static void tc27x_initfn(Object *obj)
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{
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TriCoreCPU *cpu = TRICORE_CPU(obj);
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set_feature(&cpu->env, TRICORE_FEATURE_161);
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}
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static void tc37x_initfn(Object *obj)
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{
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TriCoreCPU *cpu = TRICORE_CPU(obj);
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set_feature(&cpu->env, TRICORE_FEATURE_162);
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}
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps tricore_sysemu_ops = {
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.get_phys_page_debug = tricore_cpu_get_phys_page_debug,
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};
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#include "hw/core/tcg-cpu-ops.h"
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static const TCGCPUOps tricore_tcg_ops = {
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.initialize = tricore_tcg_init,
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.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
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.restore_state_to_opc = tricore_restore_state_to_opc,
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.tlb_fill = tricore_cpu_tlb_fill,
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};
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static void tricore_cpu_class_init(ObjectClass *c, void *data)
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{
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TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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DeviceClass *dc = DEVICE_CLASS(c);
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ResettableClass *rc = RESETTABLE_CLASS(c);
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device_class_set_parent_realize(dc, tricore_cpu_realizefn,
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&mcc->parent_realize);
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resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
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&mcc->parent_phases);
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cc->class_by_name = tricore_cpu_class_by_name;
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cc->has_work = tricore_cpu_has_work;
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cc->mmu_index = tricore_cpu_mmu_index;
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cc->gdb_read_register = tricore_cpu_gdb_read_register;
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cc->gdb_write_register = tricore_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 44;
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cc->gdb_arch_name = tricore_gdb_arch_name;
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cc->dump_state = tricore_cpu_dump_state;
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cc->set_pc = tricore_cpu_set_pc;
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cc->get_pc = tricore_cpu_get_pc;
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cc->sysemu_ops = &tricore_sysemu_ops;
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cc->tcg_ops = &tricore_tcg_ops;
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}
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#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_TRICORE_CPU, \
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.instance_init = initfn, \
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.name = TRICORE_CPU_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo tricore_cpu_type_infos[] = {
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{
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.name = TYPE_TRICORE_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(TriCoreCPU),
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.instance_align = __alignof(TriCoreCPU),
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.abstract = true,
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.class_size = sizeof(TriCoreCPUClass),
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.class_init = tricore_cpu_class_init,
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},
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DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
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DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
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DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
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DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
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};
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DEFINE_TYPES(tricore_cpu_type_infos)
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