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accel/tcg: Access tcg_cflags with getter / setter

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Access the CPUState::tcg_cflags via tcg_cflags_has() and
tcg_cflags_set() helpers.

Mechanical change using the following Coccinelle spatch script:

  @@
  expression cpu;
  expression flags;
  @@
  -     cpu->tcg_cflags & flags
  +     tcg_cflags_has(cpu, flags)

  @@
  expression cpu;
  expression flags;
  @@
  -     (tcg_cflags_has(cpu, flags))
  +     tcg_cflags_has(cpu, flags)

  @@
  expression cpu;
  expression flags;
  @@
  -     cpu->tcg_cflags |= flags;
  +     tcg_cflags_set(cpu, flags);

Then manually moving the declarations, and adding both
tcg_cflags_has() and tcg_cflags_set() definitions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240427155714.53669-15-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-01-10 18:09:56 +01:00
parent 0650fc1ea3
commit b254c342cf
23 changed files with 44 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
accel/tcg/cpu-exec.c
View File

@ -147,6 +147,16 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
}
#endif /* CONFIG USER ONLY */
bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
{
return cpu->tcg_cflags & flags;
}
void tcg_cflags_set(CPUState *cpu, uint32_t flags)
{
cpu->tcg_cflags |= flags;
}
uint32_t curr_cflags(CPUState *cpu)
{
uint32_t cflags = cpu->tcg_cflags;

3
accel/tcg/internal-common.h
View File

@ -9,6 +9,7 @@
#ifndef ACCEL_TCG_INTERNAL_COMMON_H
#define ACCEL_TCG_INTERNAL_COMMON_H
#include "exec/cpu-common.h"
#include "exec/translation-block.h"
extern int64_t max_delay;
@ -20,7 +21,7 @@ extern int64_t max_advance;
*/
static inline bool cpu_in_serial_context(CPUState *cs)
{
return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs);
return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs);
}
#endif

2
accel/tcg/tcg-accel-ops.c
View File

@ -62,7 +62,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
cflags |= parallel ? CF_PARALLEL : 0;
cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
cpu->tcg_cflags |= cflags;
tcg_cflags_set(cpu, cflags);
}
void tcg_cpu_destroy(CPUState *cpu)

7
include/exec/cpu-common.h
View File

@ -178,6 +178,13 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void list_cpus(void);
#ifdef CONFIG_TCG
bool tcg_cflags_has(CPUState *cpu, uint32_t flags);
void tcg_cflags_set(CPUState *cpu, uint32_t flags);
/* current cflags for hashing/comparison */
uint32_t curr_cflags(CPUState *cpu);
/**
* cpu_unwind_state_data:
* @cpu: the cpu context

3
include/exec/exec-all.h
View File

@ -510,9 +510,6 @@ static inline void tb_set_page_addr1(TranslationBlock *tb,
#endif
}
/* current cflags for hashing/comparison */
uint32_t curr_cflags(CPUState *cpu);
/* TranslationBlock invalidate API */
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);

8
linux-user/mmap.c
View File

@ -960,8 +960,8 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot,
*/
if (ret != -1 && (flags & MAP_TYPE) != MAP_PRIVATE) {
CPUState *cpu = thread_cpu;
if (!(cpu->tcg_cflags & CF_PARALLEL)) {
cpu->tcg_cflags |= CF_PARALLEL;
if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}
}
@ -1400,8 +1400,8 @@ abi_ulong target_shmat(CPUArchState *cpu_env, int shmid,
* supported by the host -- anything that requires EXCP_ATOMIC will not
* be atomic with respect to an external process.
*/
if (!(cpu->tcg_cflags & CF_PARALLEL)) {
cpu->tcg_cflags |= CF_PARALLEL;
if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}

4
linux-user/syscall.c
View File

@ -6583,8 +6583,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
* generate code for parallel execution and flush old translations.
* Do this now so that the copy gets CF_PARALLEL too.
*/
if (!(cpu->tcg_cflags & CF_PARALLEL)) {
cpu->tcg_cflags |= CF_PARALLEL;
if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}

2
target/arm/cpu.c
View File

@ -1941,7 +1941,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
/* Use pc-relative instructions in system-mode */
cs->tcg_cflags |= CF_PCREL;
tcg_cflags_set(cs, CF_PCREL);
#endif
/* If we needed to query the host kernel for the CPU features

2
target/avr/cpu.c
View File

@ -55,7 +55,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
static void avr_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */
}

2
target/hexagon/cpu.c
View File

@ -257,7 +257,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs)
static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
}

2
target/hppa/cpu.c
View File

@ -48,7 +48,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
{
HPPACPU *cpu = HPPA_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
#ifdef CONFIG_USER_ONLY
cpu->env.iaoq_f = tb->pc;

2
target/i386/cpu.c
View File

@ -7371,7 +7371,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
/* Use pc-relative instructions in system-mode */
cs->tcg_cflags |= CF_PCREL;
tcg_cflags_set(cs, CF_PCREL);
#endif
if (cpu->apic_id == UNASSIGNED_APIC_ID) {

2
target/i386/helper.c
View File

@ -523,7 +523,7 @@ static inline target_ulong get_memio_eip(CPUX86State *env)
}
/* Per x86_restore_state_to_opc. */
if (cs->tcg_cflags & CF_PCREL) {
if (tcg_cflags_has(cs, CF_PCREL)) {
return (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
return data[0] - env->segs[R_CS].base;

2
target/loongarch/cpu.c
View File

@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
set_pc(cpu_env(cs), tb->pc);
}

2
target/microblaze/cpu.c
View File

@ -99,7 +99,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
}

2
target/mips/tcg/exception.c
View File

@ -81,7 +81,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
{
CPUMIPSState *env = cpu_env(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;

2
target/mips/tcg/sysemu/special_helper.c
View File

@ -93,7 +93,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
CPUMIPSState *env = cpu_env(cs);
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
&& !tcg_cflags_has(cs, CF_PCREL) && env->active_tc.PC != tb->pc) {
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
env->hflags &= ~MIPS_HFLAG_BMASK;
return true;

2
target/openrisc/cpu.c
View File

@ -45,7 +45,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
}

4
target/riscv/tcg/tcg-cpu.c
View File

@ -96,7 +96,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
if (xl == MXL_RV32) {
env->pc = (int32_t) tb->pc;
@ -890,7 +890,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
CPU(cs)->tcg_cflags |= CF_PCREL;
tcg_cflags_set(CPU(cs), CF_PCREL);
if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);

2
target/rx/cpu.c
View File

@ -46,7 +46,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
{
RXCPU *cpu = RX_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
}

4
target/sh4/cpu.c
View File

@ -47,7 +47,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
{
SuperHCPU *cpu = SUPERH_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
}
@ -74,7 +74,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
CPUSH4State *env = cpu_env(cs);
if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
&& !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) {
&& !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) {
env->pc -= 2;
env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
return true;

2
target/sparc/cpu.c
View File

@ -702,7 +702,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
{
SPARCCPU *cpu = SPARC_CPU(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.npc = tb->cs_base;
}

2
target/tricore/cpu.c
View File

@ -47,7 +47,7 @@ static vaddr tricore_cpu_get_pc(CPUState *cs)
static void tricore_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->PC = tb->pc;
}