Bastian Koppelmann 25e6ca30c6 target/riscv: Remove decode_RV32_64G() ...

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>

2019-03-13 10:40:50 +01:00

..

insn_trans

target/riscv: Rename trans_arith to gen_arith

2019-03-13 10:40:50 +01:00

cpu_bits.h

RISC-V: Add misa runtime write support

2019-02-11 15:56:22 -08:00

cpu_helper.c

RISC-V: Use riscv prefix consistently on cpu helpers

2019-02-11 15:56:21 -08:00

cpu_user.h

…

cpu.c

RISC-V: Add misa runtime write support

2019-02-11 15:56:22 -08:00

cpu.h

RISC-V: Add misa runtime write support

2019-02-11 15:56:22 -08:00

csr.c

target/riscv: fix counter-enable checks in ctr()

2019-02-11 15:56:22 -08:00

fpu_helper.c

RISC-V: Use riscv prefix consistently on cpu helpers

2019-02-11 15:56:21 -08:00

gdbstub.c

…

helper.h

…

insn16.decode

target/riscv: Convert quadrant 2 of RVXC insns to decodetree

2019-03-13 10:40:46 +01:00

insn32-64.decode

target/riscv: Convert RV64D insns to decodetree

2019-03-13 10:34:06 +01:00

insn32.decode

target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

2019-03-13 10:40:50 +01:00

instmap.h

…

Makefile.objs

target/riscv: Convert quadrant 0 of RVXC insns to decodetree

2019-03-13 10:34:06 +01:00

op_helper.c

RISC-V: Use riscv prefix consistently on cpu helpers

2019-02-11 15:56:21 -08:00

pmp.c

…

pmp.h

…

translate.c

target/riscv: Remove decode_RV32_64G()

2019-03-13 10:40:50 +01:00