4921a0ce86
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory. Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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.. | ||
boot.c | ||
Kconfig | ||
meson.build | ||
microchip_pfsoc.c | ||
numa.c | ||
opentitan.c | ||
riscv_hart.c | ||
riscv_htif.c | ||
sifive_clint.c | ||
sifive_e.c | ||
sifive_plic.c | ||
sifive_test.c | ||
sifive_u.c | ||
sifive_uart.c | ||
spike.c | ||
virt.c |