qemu/target
Philippe Mathieu-Daudé 2412813286 target/arm: Ensure icount is enabled when emulating INST_RETIRED
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.

PMU events are TCG-only, hardware accelerators handle them
directly. Unfortunately we register the events in non-TCG builds,
leading to linking error such:

  ld: Undefined symbols:
    _icount_to_ns, referenced from:
      _instructions_ns_per in target_arm_helper.c.o
  clang: error: linker command failed with exit code 1 (use -v to see invocation)

As a kludge, give a hint to the compiler by asserting the
pm_event::get_count() and pm_event::ns_per_count() handler will
only be called under this icount mode.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231208113529.74067-5-philmd@linaro.org>
2024-01-19 12:28:59 +01:00
..
alpha target/alpha: Only build sys_helper.c on system emulation 2024-01-19 12:28:59 +01:00
arm target/arm: Ensure icount is enabled when emulating INST_RETIRED 2024-01-19 12:28:59 +01:00
avr target/avr: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
cris target/cris: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hexagon target/hexagon: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hppa target/hppa qemu v8.2 regression fixes 2024-01-16 14:24:42 +00:00
i386 accel: Do not set CPUState::tcg_cflags in non-TCG accels 2024-01-19 12:28:59 +01:00
loongarch hw/loongarch/virt: Set iocsr address space per-board rather than percpu 2024-01-11 19:22:47 +08:00
m68k target/m68k: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
microblaze target/microblaze: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
mips system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
nios2 target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
openrisc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
ppc qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD 2024-01-08 10:45:43 -05:00
riscv target/riscv: Ensure mideleg is set correctly on reset 2024-01-10 18:47:47 +10:00
rx target/rx: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
s390x target/s390x: Fix LAE setting a wrong access register 2024-01-11 14:13:07 +01:00
sh4 target/sh4: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
sparc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
tricore target/tricore: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
xtensa target/xtensa: use generic instruction breakpoint infrastructure 2024-01-19 12:28:59 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00