target/xtensa: use generic instruction breakpoint infrastructure
Don't embed ibreak exception generation into TB and don't invalidate TB on ibreak address change. Add CPUBreakpoint pointers to xtensa CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint callback that recognizes valid instruction breakpoints. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231130171920.3798954-2-jcmvbkbc@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
parent
396f66f99d
commit
5f3ebbc86d
@ -233,6 +233,7 @@ static const struct TCGCPUOps xtensa_tcg_ops = {
|
||||
.do_interrupt = xtensa_cpu_do_interrupt,
|
||||
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
|
||||
.do_unaligned_access = xtensa_cpu_do_unaligned_access,
|
||||
.debug_check_breakpoint = xtensa_debug_check_breakpoint,
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
};
|
||||
|
||||
|
@ -229,6 +229,7 @@ enum {
|
||||
#define MAX_NCCOMPARE 3
|
||||
#define MAX_TLB_WAY_SIZE 8
|
||||
#define MAX_NDBREAK 2
|
||||
#define MAX_NIBREAK 2
|
||||
#define MAX_NMEMORY 4
|
||||
#define MAX_MPU_FOREGROUND_SEGMENTS 32
|
||||
|
||||
@ -547,6 +548,8 @@ struct CPUArchState {
|
||||
|
||||
/* Watchpoints for DBREAK registers */
|
||||
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
|
||||
/* Breakpoints for IBREAK registers */
|
||||
struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK];
|
||||
};
|
||||
|
||||
/**
|
||||
@ -590,6 +593,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr);
|
||||
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
bool xtensa_debug_check_breakpoint(CPUState *cs);
|
||||
#endif
|
||||
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
|
||||
void xtensa_count_regs(const XtensaConfig *config,
|
||||
|
@ -33,27 +33,21 @@
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/address-spaces.h"
|
||||
|
||||
static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
|
||||
{
|
||||
uint32_t paddr;
|
||||
uint32_t page_size;
|
||||
unsigned access;
|
||||
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
|
||||
&paddr, &page_size, &access);
|
||||
if (ret == 0) {
|
||||
tb_invalidate_phys_addr(&address_space_memory, paddr,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
uint32_t change = v ^ env->sregs[IBREAKENABLE];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < env->config->nibreak; ++i) {
|
||||
if (change & (1 << i)) {
|
||||
tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
|
||||
if (v & (1 << i)) {
|
||||
cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i],
|
||||
BP_CPU, &env->cpu_breakpoint[i]);
|
||||
} else {
|
||||
cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]);
|
||||
env->cpu_breakpoint[i] = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
|
||||
@ -62,12 +56,32 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
|
||||
void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
|
||||
{
|
||||
if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
|
||||
tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
|
||||
tb_invalidate_virtual_addr(env, v);
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]);
|
||||
cpu_breakpoint_insert(cs, v, BP_CPU, &env->cpu_breakpoint[i]);
|
||||
}
|
||||
env->sregs[IBREAKA + i] = v;
|
||||
}
|
||||
|
||||
bool xtensa_debug_check_breakpoint(CPUState *cs)
|
||||
{
|
||||
XtensaCPU *cpu = XTENSA_CPU(cs);
|
||||
CPUXtensaState *env = &cpu->env;
|
||||
unsigned int i;
|
||||
|
||||
if (xtensa_get_cintlevel(env) >= env->config->debug_level) {
|
||||
return false;
|
||||
}
|
||||
for (i = 0; i < env->config->nibreak; ++i) {
|
||||
if (env->sregs[IBREAKENABLE] & (1 << i) &&
|
||||
env->sregs[IBREAKA + i] == env->pc) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
|
||||
uint32_t dbreakc)
|
||||
{
|
||||
|
@ -231,6 +231,18 @@ void xtensa_breakpoint_handler(CPUState *cs)
|
||||
}
|
||||
cpu_loop_exit_noexc(cs);
|
||||
}
|
||||
} else {
|
||||
if (cpu_breakpoint_test(cs, env->pc, BP_GDB)
|
||||
|| !cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
|
||||
return;
|
||||
}
|
||||
if (env->sregs[ICOUNT] == 0xffffffff &&
|
||||
xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
|
||||
debug_exception_env(env, DEBUGCAUSE_IC);
|
||||
} else {
|
||||
debug_exception_env(env, DEBUGCAUSE_IB);
|
||||
}
|
||||
cpu_loop_exit_noexc(cs);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1123,19 +1123,6 @@ static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
|
||||
return xtensa_op0_insn_len(dc, b0);
|
||||
}
|
||||
|
||||
static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < dc->config->nibreak; ++i) {
|
||||
if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
|
||||
env->sregs[IBREAKA + i] == dc->pc) {
|
||||
gen_debug_exception(dc, DEBUGCAUSE_IB);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
|
||||
CPUState *cpu)
|
||||
{
|
||||
@ -1205,10 +1192,6 @@ static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
||||
gen_set_label(label);
|
||||
}
|
||||
|
||||
if (dc->debug) {
|
||||
gen_ibreak_check(env, dc);
|
||||
}
|
||||
|
||||
disas_xtensa_insn(env, dc);
|
||||
|
||||
if (dc->icount) {
|
||||
|
Loading…
Reference in New Issue
Block a user