3aa597f650
sPAPRXive models the XIVE interrupt controller of the sPAPR machine. It inherits from the XiveRouter and provisions storage for the routing tables : - Event Assignment Structure (EAS) - Event Notification Descriptor (END) The sPAPRXive model incorporates an internal XiveSource for the IPIs and for the interrupts of the virtual devices of the guest. This model is consistent with XIVE architecture which also incorporates an internal IVSE for IPIs and accelerator interrupts in the IVRE sub-engine. The sPAPRXive model exports two memory regions, one for the ESB trigger and management pages used to control the sources and one for the TIMA pages. They are mapped by default at the addresses found on chip 0 of a baremetal system. This is also consistent with the XIVE architecture which defines a Virtualization Controller BAR for the internal IVSE ESB pages and a Thread Managment BAR for the TIMA. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Fold in field accessor fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
24 lines
501 B
Makefile
24 lines
501 B
Makefile
# Default configuration for ppc64-softmmu
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# Include all 32-bit boards
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include ppc-softmmu.mak
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# For PowerNV
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CONFIG_POWERNV=y
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CONFIG_IPMI=y
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CONFIG_IPMI_LOCAL=y
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CONFIG_IPMI_EXTERN=y
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CONFIG_ISA_IPMI_BT=y
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# For pSeries
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CONFIG_PSERIES=y
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CONFIG_VIRTIO_VGA=y
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CONFIG_XICS=$(CONFIG_PSERIES)
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CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
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CONFIG_XICS_KVM=$(call land,$(CONFIG_PSERIES),$(CONFIG_KVM))
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CONFIG_XIVE=$(CONFIG_PSERIES)
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CONFIG_XIVE_SPAPR=$(CONFIG_PSERIES)
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CONFIG_MEM_DEVICE=y
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CONFIG_DIMM=y
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CONFIG_SPAPR_RNG=y
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