spapr/xive: introduce a XIVE interrupt controller
sPAPRXive models the XIVE interrupt controller of the sPAPR machine. It inherits from the XiveRouter and provisions storage for the routing tables : - Event Assignment Structure (EAS) - Event Notification Descriptor (END) The sPAPRXive model incorporates an internal XiveSource for the IPIs and for the interrupts of the virtual devices of the guest. This model is consistent with XIVE architecture which also incorporates an internal IVSE for IPIs and accelerator interrupts in the IVRE sub-engine. The sPAPRXive model exports two memory regions, one for the ESB trigger and management pages used to control the sources and one for the TIMA pages. They are mapped by default at the addresses found on chip 0 of a baremetal system. This is also consistent with the XIVE architecture which defines a Virtualization Controller BAR for the internal IVSE ESB pages and a Thread Managment BAR for the TIMA. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Fold in field accessor fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
cdd4de68ed
commit
3aa597f650
@ -17,6 +17,7 @@ CONFIG_XICS=$(CONFIG_PSERIES)
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CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
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CONFIG_XICS_KVM=$(call land,$(CONFIG_PSERIES),$(CONFIG_KVM))
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CONFIG_XIVE=$(CONFIG_PSERIES)
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CONFIG_XIVE_SPAPR=$(CONFIG_PSERIES)
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CONFIG_MEM_DEVICE=y
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CONFIG_DIMM=y
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CONFIG_SPAPR_RNG=y
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@ -38,6 +38,7 @@ obj-$(CONFIG_XICS) += xics.o
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obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
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obj-$(CONFIG_XICS_KVM) += xics_kvm.o
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obj-$(CONFIG_XIVE) += xive.o
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obj-$(CONFIG_XIVE_SPAPR) += spapr_xive.o
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obj-$(CONFIG_POWERNV) += xics_pnv.o
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obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
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obj-$(CONFIG_S390_FLIC) += s390_flic.o
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366
hw/intc/spapr_xive.c
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366
hw/intc/spapr_xive.c
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@ -0,0 +1,366 @@
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/*
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* QEMU PowerPC sPAPR XIVE interrupt controller model
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "target/ppc/cpu.h"
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#include "sysemu/cpus.h"
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#include "monitor/monitor.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_xive.h"
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#include "hw/ppc/xive.h"
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#include "hw/ppc/xive_regs.h"
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/*
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* XIVE Virtualization Controller BAR and Thread Managment BAR that we
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* use for the ESB pages and the TIMA pages
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*/
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#define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
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#define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
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/*
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* On sPAPR machines, use a simplified output for the XIVE END
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* structure dumping only the information related to the OS EQ.
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*/
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static void spapr_xive_end_pic_print_info(sPAPRXive *xive, XiveEND *end,
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Monitor *mon)
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{
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uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
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uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1);
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uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
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uint32_t qentries = 1 << (qsize + 10);
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uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6);
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uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7);
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monitor_printf(mon, "%3d/%d % 6d/%5d ^%d", nvt,
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priority, qindex, qentries, qgen);
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xive_end_queue_pic_print_info(end, 6, mon);
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monitor_printf(mon, "]");
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}
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void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon)
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{
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XiveSource *xsrc = &xive->source;
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int i;
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monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n");
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for (i = 0; i < xive->nr_irqs; i++) {
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uint8_t pq = xive_source_esb_get(xsrc, i);
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XiveEAS *eas = &xive->eat[i];
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if (!xive_eas_is_valid(eas)) {
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continue;
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}
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monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i,
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xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
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pq & XIVE_ESB_VAL_P ? 'P' : '-',
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pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
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xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ',
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xive_eas_is_masked(eas) ? "M" : " ",
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(int) xive_get_field64(EAS_END_DATA, eas->w));
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if (!xive_eas_is_masked(eas)) {
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uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w);
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XiveEND *end;
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assert(end_idx < xive->nr_ends);
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end = &xive->endt[end_idx];
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if (xive_end_is_valid(end)) {
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spapr_xive_end_pic_print_info(xive, end, mon);
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}
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}
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monitor_printf(mon, "\n");
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}
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}
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static void spapr_xive_map_mmio(sPAPRXive *xive)
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{
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sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base);
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sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base);
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sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base);
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}
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static void spapr_xive_end_reset(XiveEND *end)
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{
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memset(end, 0, sizeof(*end));
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/* switch off the escalation and notification ESBs */
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end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q);
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}
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static void spapr_xive_reset(void *dev)
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{
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sPAPRXive *xive = SPAPR_XIVE(dev);
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int i;
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/*
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* The XiveSource has its own reset handler, which mask off all
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* IRQs (!P|Q)
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*/
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/* Mask all valid EASs in the IRQ number space. */
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for (i = 0; i < xive->nr_irqs; i++) {
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XiveEAS *eas = &xive->eat[i];
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if (xive_eas_is_valid(eas)) {
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eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED);
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} else {
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eas->w = 0;
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}
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}
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/* Clear all ENDs */
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for (i = 0; i < xive->nr_ends; i++) {
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spapr_xive_end_reset(&xive->endt[i]);
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}
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}
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static void spapr_xive_instance_init(Object *obj)
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{
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sPAPRXive *xive = SPAPR_XIVE(obj);
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object_initialize(&xive->source, sizeof(xive->source), TYPE_XIVE_SOURCE);
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object_property_add_child(obj, "source", OBJECT(&xive->source), NULL);
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object_initialize(&xive->end_source, sizeof(xive->end_source),
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TYPE_XIVE_END_SOURCE);
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object_property_add_child(obj, "end_source", OBJECT(&xive->end_source),
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NULL);
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}
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static void spapr_xive_realize(DeviceState *dev, Error **errp)
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{
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sPAPRXive *xive = SPAPR_XIVE(dev);
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XiveSource *xsrc = &xive->source;
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XiveENDSource *end_xsrc = &xive->end_source;
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Error *local_err = NULL;
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if (!xive->nr_irqs) {
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error_setg(errp, "Number of interrupt needs to be greater 0");
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return;
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}
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if (!xive->nr_ends) {
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error_setg(errp, "Number of interrupt needs to be greater 0");
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return;
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}
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/*
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* Initialize the internal sources, for IPIs and virtual devices.
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*/
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object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs",
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&error_fatal);
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object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive),
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&error_fatal);
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object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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/*
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* Initialize the END ESB source
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*/
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object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends",
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&error_fatal);
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object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
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&error_fatal);
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object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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/* Set the mapping address of the END ESB pages after the source ESBs */
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xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
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/*
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* Allocate the routing tables
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*/
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xive->eat = g_new0(XiveEAS, xive->nr_irqs);
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xive->endt = g_new0(XiveEND, xive->nr_ends);
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/* TIMA initialization */
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memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive,
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"xive.tima", 4ull << TM_SHIFT);
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/* Define all XIVE MMIO regions on SysBus */
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sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio);
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sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio);
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sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
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/* Map all regions */
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spapr_xive_map_mmio(xive);
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qemu_register_reset(spapr_xive_reset, dev);
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}
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static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk,
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uint32_t eas_idx, XiveEAS *eas)
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{
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sPAPRXive *xive = SPAPR_XIVE(xrtr);
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if (eas_idx >= xive->nr_irqs) {
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return -1;
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}
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*eas = xive->eat[eas_idx];
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return 0;
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}
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static int spapr_xive_get_end(XiveRouter *xrtr,
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uint8_t end_blk, uint32_t end_idx, XiveEND *end)
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{
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sPAPRXive *xive = SPAPR_XIVE(xrtr);
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if (end_idx >= xive->nr_ends) {
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return -1;
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}
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memcpy(end, &xive->endt[end_idx], sizeof(XiveEND));
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return 0;
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}
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static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk,
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uint32_t end_idx, XiveEND *end,
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uint8_t word_number)
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{
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sPAPRXive *xive = SPAPR_XIVE(xrtr);
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if (end_idx >= xive->nr_ends) {
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return -1;
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}
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memcpy(&xive->endt[end_idx], end, sizeof(XiveEND));
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return 0;
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}
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static const VMStateDescription vmstate_spapr_xive_end = {
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.name = TYPE_SPAPR_XIVE "/end",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(w0, XiveEND),
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VMSTATE_UINT32(w1, XiveEND),
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VMSTATE_UINT32(w2, XiveEND),
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VMSTATE_UINT32(w3, XiveEND),
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VMSTATE_UINT32(w4, XiveEND),
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VMSTATE_UINT32(w5, XiveEND),
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VMSTATE_UINT32(w6, XiveEND),
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VMSTATE_UINT32(w7, XiveEND),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_spapr_xive_eas = {
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.name = TYPE_SPAPR_XIVE "/eas",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT64(w, XiveEAS),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_spapr_xive = {
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.name = TYPE_SPAPR_XIVE,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL),
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, sPAPRXive, nr_irqs,
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vmstate_spapr_xive_eas, XiveEAS),
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, sPAPRXive, nr_ends,
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vmstate_spapr_xive_end, XiveEND),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property spapr_xive_properties[] = {
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DEFINE_PROP_UINT32("nr-irqs", sPAPRXive, nr_irqs, 0),
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DEFINE_PROP_UINT32("nr-ends", sPAPRXive, nr_ends, 0),
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DEFINE_PROP_UINT64("vc-base", sPAPRXive, vc_base, SPAPR_XIVE_VC_BASE),
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DEFINE_PROP_UINT64("tm-base", sPAPRXive, tm_base, SPAPR_XIVE_TM_BASE),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void spapr_xive_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
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dc->desc = "sPAPR XIVE Interrupt Controller";
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dc->props = spapr_xive_properties;
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dc->realize = spapr_xive_realize;
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dc->vmsd = &vmstate_spapr_xive;
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xrc->get_eas = spapr_xive_get_eas;
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xrc->get_end = spapr_xive_get_end;
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xrc->write_end = spapr_xive_write_end;
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}
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static const TypeInfo spapr_xive_info = {
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.name = TYPE_SPAPR_XIVE,
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.parent = TYPE_XIVE_ROUTER,
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.instance_init = spapr_xive_instance_init,
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.instance_size = sizeof(sPAPRXive),
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.class_init = spapr_xive_class_init,
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};
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static void spapr_xive_register_types(void)
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{
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type_register_static(&spapr_xive_info);
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}
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type_init(spapr_xive_register_types)
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bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi)
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{
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XiveSource *xsrc = &xive->source;
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if (lisn >= xive->nr_irqs) {
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return false;
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}
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xive->eat[lisn].w |= cpu_to_be64(EAS_VALID);
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xive_source_irq_set(xsrc, lisn, lsi);
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return true;
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}
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bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn)
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{
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XiveSource *xsrc = &xive->source;
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if (lisn >= xive->nr_irqs) {
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return false;
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}
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xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID);
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xive_source_irq_set(xsrc, lisn, false);
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return true;
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}
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qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn)
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{
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XiveSource *xsrc = &xive->source;
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if (lisn >= xive->nr_irqs) {
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return NULL;
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}
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/* The sPAPR machine/device should have claimed the IRQ before */
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assert(xive_eas_is_valid(&xive->eat[lisn]));
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return xive_source_qirq(xsrc, lisn);
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}
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45
include/hw/ppc/spapr_xive.h
Normal file
45
include/hw/ppc/spapr_xive.h
Normal file
@ -0,0 +1,45 @@
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/*
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* QEMU PowerPC sPAPR XIVE interrupt controller model
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_SPAPR_XIVE_H
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#define PPC_SPAPR_XIVE_H
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#include "hw/ppc/xive.h"
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#define TYPE_SPAPR_XIVE "spapr-xive"
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#define SPAPR_XIVE(obj) OBJECT_CHECK(sPAPRXive, (obj), TYPE_SPAPR_XIVE)
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typedef struct sPAPRXive {
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XiveRouter parent;
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/* Internal interrupt source for IPIs and virtual devices */
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XiveSource source;
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hwaddr vc_base;
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/* END ESB MMIOs */
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XiveENDSource end_source;
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hwaddr end_base;
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|
||||
/* Routing table */
|
||||
XiveEAS *eat;
|
||||
uint32_t nr_irqs;
|
||||
XiveEND *endt;
|
||||
uint32_t nr_ends;
|
||||
|
||||
/* TIMA mapping address */
|
||||
hwaddr tm_base;
|
||||
MemoryRegion tm_mmio;
|
||||
} sPAPRXive;
|
||||
|
||||
bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi);
|
||||
bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn);
|
||||
void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon);
|
||||
qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn);
|
||||
|
||||
#endif /* PPC_SPAPR_XIVE_H */
|
||||
Loading…
Reference in New Issue
Block a user