Daniel Henrique Barboza d3b96a5319 hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check ... 'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the 'switch' right before it if 'mode' isn't 0, 8, 9 or 10. 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32. Reported by Coverity via a "DEADCODE" ticket. Resolves: Coverity CID 1564781 Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-11-07 08:19:39 +10:00
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boot.c
Kconfig
meson.build
microchip_pfsoc.c
numa.c
opentitan.c
riscv_hart.c
riscv-iommu-bits.h
riscv-iommu-pci.c
riscv-iommu.c	hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check	2024-11-07 08:19:39 +10:00
riscv-iommu.h
shakti_c.c
sifive_e.c
sifive_u.c
spike.c
trace-events
trace.h
virt-acpi-build.c
virt.c