hw/riscv: add RISC-V IOMMU base emulation
The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V IOMMU. It includes support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4, sv39x4, sv48x4, sv57x4 caps). Other capabilities like ATS and DBG support will be added incrementally in the next patches. Co-developed-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jason Chien <jason.chien@sifive.com> Message-ID: <20241016204038.649340-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Tomasz Jeznach
Alistair Francis
parent
e21b3b243f
commit
0c54acb824
@ -1,3 +1,6 @@
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config RISCV_IOMMU
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bool
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config RISCV_NUMA
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bool
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@ -47,6 +50,7 @@ config RISCV_VIRT
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select SERIAL_MM
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select RISCV_ACLINT
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select RISCV_APLIC
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select RISCV_IOMMU
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select RISCV_IMSIC
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select SIFIVE_PLIC
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select SIFIVE_TEST
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@ -10,5 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c'))
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hw_arch += {'riscv': riscv_ss}
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@ -69,6 +69,14 @@ struct riscv_iommu_pq_record {
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/* 5.3 IOMMU Capabilities (64bits) */
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#define RISCV_IOMMU_REG_CAP 0x0000
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#define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0)
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#define RISCV_IOMMU_CAP_SV32 BIT_ULL(8)
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#define RISCV_IOMMU_CAP_SV39 BIT_ULL(9)
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#define RISCV_IOMMU_CAP_SV48 BIT_ULL(10)
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#define RISCV_IOMMU_CAP_SV57 BIT_ULL(11)
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#define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16)
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#define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17)
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#define RISCV_IOMMU_CAP_SV48X4 BIT_ULL(18)
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#define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19)
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#define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22)
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#define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23)
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#define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26)
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@ -80,7 +88,9 @@ struct riscv_iommu_pq_record {
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/* 5.4 Features control register (32bits) */
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#define RISCV_IOMMU_REG_FCTL 0x0008
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#define RISCV_IOMMU_FCTL_BE BIT(0)
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#define RISCV_IOMMU_FCTL_WSI BIT(1)
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#define RISCV_IOMMU_FCTL_GXL BIT(2)
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/* 5.5 Device-directory-table pointer (64bits) */
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#define RISCV_IOMMU_REG_DDTP 0x0010
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@ -175,6 +185,10 @@ enum {
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/* 5.27 Interrupt cause to vector (64bits) */
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#define RISCV_IOMMU_REG_ICVEC 0x02F8
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#define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0)
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#define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4)
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#define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8)
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#define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12)
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/* 5.28 MSI Configuration table (32 * 64bits) */
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#define RISCV_IOMMU_REG_MSI_CONFIG 0x0300
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@ -203,6 +217,8 @@ struct riscv_iommu_dc {
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#define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4)
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#define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5)
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#define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6)
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#define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7)
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#define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8)
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#define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9)
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#define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10)
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#define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11)
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@ -309,9 +325,11 @@ enum riscv_iommu_fq_causes {
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/* Translation attributes fields */
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#define RISCV_IOMMU_PC_TA_V BIT_ULL(0)
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#define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32)
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/* First stage context fields */
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#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0)
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#define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44)
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enum riscv_iommu_fq_ttypes {
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RISCV_IOMMU_FQ_TTYPE_NONE = 0,
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2021
hw/riscv/riscv-iommu.c
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2021
hw/riscv/riscv-iommu.c
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File diff suppressed because it is too large
Load Diff
126
hw/riscv/riscv-iommu.h
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126
hw/riscv/riscv-iommu.h
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@ -0,0 +1,126 @@
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/*
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* QEMU emulation of an RISC-V IOMMU
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_STATE_H
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#define HW_RISCV_IOMMU_STATE_H
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#include "qom/object.h"
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#include "hw/riscv/iommu.h"
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struct RISCVIOMMUState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t version; /* Reported interface version number */
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uint32_t pid_bits; /* process identifier width */
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uint32_t bus; /* PCI bus mapping for non-root endpoints */
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uint64_t cap; /* IOMMU supported capabilities */
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uint64_t fctl; /* IOMMU enabled features */
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uint64_t icvec_avail_vectors; /* Available interrupt vectors in ICVEC */
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bool enable_off; /* Enable out-of-reset OFF mode (DMA disabled) */
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bool enable_msi; /* Enable MSI remapping */
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bool enable_s_stage; /* Enable S/VS-Stage translation */
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bool enable_g_stage; /* Enable G-Stage translation */
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/* IOMMU Internal State */
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uint64_t ddtp; /* Validated Device Directory Tree Root Pointer */
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dma_addr_t cq_addr; /* Command queue base physical address */
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dma_addr_t fq_addr; /* Fault/event queue base physical address */
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dma_addr_t pq_addr; /* Page request queue base physical address */
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uint32_t cq_mask; /* Command queue index bit mask */
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uint32_t fq_mask; /* Fault/event queue index bit mask */
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uint32_t pq_mask; /* Page request queue index bit mask */
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/* interrupt notifier */
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void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
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/* IOMMU State Machine */
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QemuThread core_proc; /* Background processing thread */
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QemuCond core_cond; /* Background processing wake up signal */
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unsigned core_exec; /* Processing thread execution actions */
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/* IOMMU target address space */
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AddressSpace *target_as;
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MemoryRegion *target_mr;
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/* MSI / MRIF access trap */
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AddressSpace trap_as;
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MemoryRegion trap_mr;
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GHashTable *ctx_cache; /* Device translation Context Cache */
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/* MMIO Hardware Interface */
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MemoryRegion regs_mr;
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uint8_t *regs_rw; /* register state (user write) */
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uint8_t *regs_wc; /* write-1-to-clear mask */
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uint8_t *regs_ro; /* read-only mask */
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QLIST_ENTRY(RISCVIOMMUState) iommus;
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QLIST_HEAD(, RISCVIOMMUSpace) spaces;
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};
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void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
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Error **errp);
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/* private helpers */
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/* Register helper functions */
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static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s,
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unsigned idx, uint32_t set, uint32_t clr)
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{
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uint32_t val = ldl_le_p(s->regs_rw + idx);
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stl_le_p(s->regs_rw + idx, (val & ~clr) | set);
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return val;
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}
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static inline void riscv_iommu_reg_set32(RISCVIOMMUState *s, unsigned idx,
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uint32_t set)
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{
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stl_le_p(s->regs_rw + idx, set);
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}
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static inline uint32_t riscv_iommu_reg_get32(RISCVIOMMUState *s, unsigned idx)
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{
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return ldl_le_p(s->regs_rw + idx);
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}
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static inline uint64_t riscv_iommu_reg_mod64(RISCVIOMMUState *s, unsigned idx,
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uint64_t set, uint64_t clr)
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{
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uint64_t val = ldq_le_p(s->regs_rw + idx);
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stq_le_p(s->regs_rw + idx, (val & ~clr) | set);
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return val;
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}
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static inline void riscv_iommu_reg_set64(RISCVIOMMUState *s, unsigned idx,
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uint64_t set)
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{
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stq_le_p(s->regs_rw + idx, set);
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}
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static inline uint64_t riscv_iommu_reg_get64(RISCVIOMMUState *s,
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unsigned idx)
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{
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return ldq_le_p(s->regs_rw + idx);
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}
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#endif
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14
hw/riscv/trace-events
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14
hw/riscv/trace-events
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@ -0,0 +1,14 @@
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# See documentation at docs/devel/tracing.rst
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# riscv-iommu.c
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riscv_iommu_new(const char *id, unsigned b, unsigned d, unsigned f) "%s: device attached %04x:%02x.%d"
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riscv_iommu_flt(const char *id, unsigned b, unsigned d, unsigned f, uint64_t reason, uint64_t iova) "%s: fault %04x:%02x.%u reason: 0x%"PRIx64" iova: 0x%"PRIx64
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riscv_iommu_pri(const char *id, unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: page request %04x:%02x.%u iova: 0x%"PRIx64
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riscv_iommu_dma(const char *id, unsigned b, unsigned d, unsigned f, unsigned pasid, const char *dir, uint64_t iova, uint64_t phys) "%s: translate %04x:%02x.%u #%u %s 0x%"PRIx64" -> 0x%"PRIx64
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riscv_iommu_msi(const char *id, unsigned b, unsigned d, unsigned f, uint64_t iova, uint64_t phys) "%s: translate %04x:%02x.%u MSI 0x%"PRIx64" -> 0x%"PRIx64
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riscv_iommu_mrif_notification(const char *id, uint32_t nid, uint64_t phys) "%s: sent MRIF notification 0x%x to 0x%"PRIx64
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riscv_iommu_cmd(const char *id, uint64_t l, uint64_t u) "%s: command 0x%"PRIx64" 0x%"PRIx64
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riscv_iommu_notifier_add(const char *id) "%s: dev-iotlb notifier added"
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riscv_iommu_notifier_del(const char *id) "%s: dev-iotlb notifier removed"
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riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector) "Interrupt cause 0x%x sent via vector 0x%x"
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riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "ICVEC write: incoming 0x%x actual 0x%x"
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1
hw/riscv/trace.h
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1
hw/riscv/trace.h
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@ -0,0 +1 @@
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#include "trace/trace-hw_riscv.h"
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36
include/hw/riscv/iommu.h
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36
include/hw/riscv/iommu.h
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@ -0,0 +1,36 @@
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/*
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* QEMU emulation of an RISC-V IOMMU
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_H
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#define HW_RISCV_IOMMU_H
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#include "qemu/osdep.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IOMMU "riscv-iommu"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUState, RISCV_IOMMU)
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typedef struct RISCVIOMMUState RISCVIOMMUState;
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#define TYPE_RISCV_IOMMU_MEMORY_REGION "riscv-iommu-mr"
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typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
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#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
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typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
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#endif
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@ -3475,6 +3475,7 @@ if have_system
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'hw/pci-host',
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'hw/ppc',
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'hw/rtc',
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'hw/riscv',
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'hw/s390x',
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'hw/scsi',
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'hw/sd',
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