a10b9d93ec
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org> |
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| .. | ||
| trans_privileged.c.inc | ||
| trans_rva.c.inc | ||
| trans_rvd.c.inc | ||
| trans_rvf.c.inc | ||
| trans_rvh.c.inc | ||
| trans_rvi.c.inc | ||
| trans_rvm.c.inc | ||
| trans_rvv.c.inc | ||