Michael Roth 417ece33fc spapr: improve ibm,architecture-vec-5 property handling ... ibm,architecture-vec-5 is supposed to encode all option vector 5 bits negotiated between platform/guest. Currently we hardcode this property in the boot-time device tree to advertise a single negotiated capability, "Form 1" NUMA Affinity, regardless of whether or not CAS has been invoked or that capability has actually been negotiated. Improve this by generating ibm,architecture-vec-5 based on the full set of option vector 5 capabilities negotiated via CAS. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2016-10-28 09:38:26 +11:00
..
block	block: More operations for meta dirty bitmap	2016-10-24 17:56:07 +02:00
crypto	crypto: add CTR mode support	2016-10-19 10:09:24 +01:00
disas
exec	tcg: Add EXCP_ATOMIC	2016-10-26 08:29:00 -07:00
fpu
hw	spapr: improve ibm,architecture-vec-5 property handling	2016-10-28 09:38:26 +11:00
io
libdecnumber
migration	migrate: move max-bandwidth and downtime-limit to migrate_set_parameter	2016-10-13 17:23:53 +02:00
monitor
net
qapi	qdict: implement a qdict_crumple method for un-flattening a dict	2016-10-25 17:56:14 +02:00
qemu	tcg: Add atomic128 helpers	2016-10-26 08:29:01 -07:00
qom	exec: call cpu_exec_exit() from a CPU unrealize common function	2016-10-24 17:29:16 -02:00
standard-headers
sysemu	Increase MAX_CPUMASK_BITS from 255 to 288	2016-10-24 17:29:15 -02:00
ui
elf.h
glib-compat.h
qemu-common.h	tcg: Add EXCP_ATOMIC	2016-10-26 08:29:00 -07:00
qemu-io.h
trace-tcg.h
trace.h