Bin Meng 406fafd5d0 hw/riscv: Move sifive_clint model to hw/intc ... This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_clint model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-09-09 15:54:19 -07:00
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boot.c	RISC-V: Support 64 bit start address	2020-07-13 17:25:37 -07:00
Kconfig	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
meson.build	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_e.c	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
sifive_plic.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_test.c	riscv: sifive_test: Allow 16-bit writes to memory region	2020-09-09 15:54:18 -07:00
sifive_u.c	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00
virt.c	hw/riscv: Move sifive_clint model to hw/intc	2020-09-09 15:54:19 -07:00