qemu/include/hw/arm
Ninad Palsule 3fd941f3f1 hw/arm: Hook up FSI module in AST2600
This patchset introduces IBM's Flexible Service Interface(FSI).

Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.

FSI has long existed in POWER processes and so comes with some baggage,
including how it has been integrated into the ASPEED SoC.

Working backwards from the POWER processor, the fundamental pieces of
interest for the implementation are:

1. The Common FRU Access Macro (CFAM), an address space containing
   various "engines" that drive accesses on buses internal and external
   to the POWER chip. Examples include the SBEFIFO and I2C masters. The
   engines hang off of an internal Local Bus (LBUS) which is described
   by the CFAM configuration block.

2. The FSI slave: The slave is the terminal point of the FSI bus for
   FSI symbols addressed to it. Slaves can be cascaded off of one
   another. The slave's configuration registers appear in address space
   of the CFAM to which it is attached.

3. The FSI master: A controller in the platform service processor (e.g.
   BMC) driving CFAM engine accesses into the POWER chip. At the
   hardware level FSI is a bit-based protocol supporting synchronous and
   DMA-driven accesses of engines in a CFAM.

4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
   POWER processors. This now makes an appearance in the ASPEED SoC due
   to tight integration of the FSI master IP with the OPB, mainly the
   existence of an MMIO-mapping of the CFAM address straight onto a
   sub-region of the OPB address space.

5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in
   the AST2600. Hardware limitations prevent the OPB from being directly
   mapped into APB, so all accesses are indirect through the bridge.

The implementation appears as following in the qemu device tree:

    (qemu) info qtree
    bus: main-system-bus
      type System
      ...
      dev: aspeed.apb2opb, id ""
        gpio-out "sysbus-irq" 1
        mmio 000000001e79b000/0000000000001000
        bus: opb.1
          type opb
          dev: fsi.master, id ""
            bus: fsi.bus.1
              type fsi.bus
              dev: cfam.config, id ""
              dev: cfam, id ""
                bus: fsi.lbus.1
                  type lbus
                  dev: scratchpad, id ""
                    address = 0 (0x0)
        bus: opb.0
          type opb
          dev: fsi.master, id ""
            bus: fsi.bus.0
              type fsi.bus
              dev: cfam.config, id ""
              dev: cfam, id ""
                bus: fsi.lbus.0
                  type lbus
                  dev: scratchpad, id ""
                    address = 0 (0x0)

The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are attached to the CFAM's LBUS. Engine implementations
should subclass the LBusDevice and set the 'config' member of
LBusDeviceClass to match the engine's type.

CFAM designs offer a lot of flexibility, for instance it is possible for
a CFAM to be simultaneously driven from multiple FSI links. The modeling
is not so complete; it's assumed that each CFAM is attached to a single
FSI slave (as a consequence the CFAM subclasses the FSI slave).

As for FSI, its symbols and wire-protocol are not modelled at all. This
is not necessary to get FSI off the ground thanks to the mapping of the
CFAM address space onto the OPB address space - the models follow this
directly and map the CFAM memory region into the OPB's memory region.
Future work includes supporting more advanced accesses that drive the
FSI master directly rather than indirectly via the CFAM mapping, which
will require implementing the FSI state machine and methods for each of
the FSI symbols on the slave. Further down the track we can also look at
supporting the bitbanged SoftFSI drivers in Linux by extending the FSI
slave model to resolve sequences of GPIO IRQs into FSI symbols, and
calling the associated symbol method on the slave to map the access onto
the CFAM.

Testing:
    Tested by reading cfam config address 0 on rainier machine type.

    root@p10bmc:~# pdbg -a getcfam 0x0
    p0: 0x0 = 0xc0022d15

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01 08:33:18 +01:00
..
allwinner-a10.h hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
allwinner-h3.h hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
allwinner-r40.h hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board 2024-01-26 11:30:47 +00:00
armsse-version.h hw/arm/armsse: Introduce SSE subsystem version property 2021-03-08 17:20:01 +00:00
armsse.h hw/arm: Set number of MPU regions correctly for an505, an521, an524 2023-08-31 11:07:02 +01:00
armv7m.h hw/arm/armv7m: alias the NVIC "num-prio-bits" property 2024-01-09 14:42:40 +00:00
aspeed_soc.h hw/arm: Hook up FSI module in AST2600 2024-02-01 08:33:18 +01:00
aspeed.h hw/arm/aspeed: Allow machine to set UART default 2021-09-20 08:50:59 +02:00
bcm2835_peripherals.h hw: Replace qemu_or_irq typedef by OrIRQState 2023-02-27 13:27:05 +00:00
bcm2836.h
boot.h hw/arm/boot: Make write_bootloader() public as arm_write_bootloader() 2023-05-02 15:47:40 +01:00
bsa.h include/hw/arm: move BSA definitions to bsa.h 2023-10-19 14:32:13 +01:00
digic.h
exynos4210.h hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h' 2023-10-19 13:01:52 +01:00
fdt.h
fsl-imx6.h hw/arm: add PCIe to Freescale i.MX6 2024-01-26 12:23:04 +00:00
fsl-imx6ul.h fsl-imx6ul: Add various missing unimplemented devices 2024-01-26 11:30:49 +00:00
fsl-imx7.h hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
fsl-imx25.h hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
fsl-imx31.h hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
linux-boot-if.h
msf2-soc.h hw/arm/msf2-soc: Wire up refclk 2021-09-01 11:08:20 +01:00
npcm7xx.h hw/arm: Attach PSPI module to NPCM7XX SoC 2023-02-16 16:00:48 +00:00
nrf51_soc.h hw/arm/nrf51: Wire up sysclk 2021-09-01 11:08:20 +01:00
nrf51.h
omap.h hw/arm/omap: Remove unused omap_uart_attach() 2023-06-05 07:43:23 +01:00
primecell.h
pxa.h hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() 2023-10-27 12:48:57 +01:00
raspberrypi-fw-defs.h hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder 2023-10-19 13:01:52 +01:00
raspi_platform.h hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property 2023-06-19 15:27:21 +01:00
sharpsl.h
smmu-common.h hw/arm/smmuv3: Add CMDs related to stage-2 2023-05-30 15:50:16 +01:00
smmuv3.h hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 2023-05-30 15:50:16 +01:00
soc_dma.h
stm32f100_soc.h hw/arm/stm32f100: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
stm32f205_soc.h hw/arm/stm32f205: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
stm32f405_soc.h hw/arm/stm32f405: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
stm32l4x5_soc.h hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC 2024-01-15 17:12:22 +00:00
virt.h include/hw/arm: move BSA definitions to bsa.h 2023-10-19 14:32:13 +01:00
xen_arch_hvm.h hw/arm: introduce xenpvh machine 2023-06-15 16:46:47 -07:00
xlnx-versal.h hw/arm/xlnx-versal: Include missing 'cpu.h' header 2024-01-26 11:30:48 +00:00
xlnx-zynqmp.h hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00