24f91e81b6
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
189 lines
6.0 KiB
C
189 lines
6.0 KiB
C
/*
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* UniCore32 virtual CPU header
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or (at your option) any
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* later version. See the COPYING file in the top-level directory.
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*/
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#ifndef UNICORE32_CPU_H
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#define UNICORE32_CPU_H
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#define TARGET_LONG_BITS 32
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#define TARGET_PAGE_BITS 12
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define CPUArchState struct CPUUniCore32State
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#include "qemu-common.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#define NB_MMU_MODES 2
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typedef struct CPUUniCore32State {
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/* Regs for current mode. */
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uint32_t regs[32];
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/* Frequently accessed ASR bits are stored separately for efficiently.
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This contains all the other bits. Use asr_{read,write} to access
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the whole ASR. */
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uint32_t uncached_asr;
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uint32_t bsr;
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/* Banked registers. */
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uint32_t banked_bsr[6];
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uint32_t banked_r29[6];
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uint32_t banked_r30[6];
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/* asr flag cache for faster execution */
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uint32_t CF; /* 0 or 1 */
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uint32_t VF; /* V is the bit 31. All other bits are undefined */
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uint32_t NF; /* N is bit 31. All other bits are undefined. */
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uint32_t ZF; /* Z set if zero. */
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/* System control coprocessor (cp0) */
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struct {
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uint32_t c0_cpuid;
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uint32_t c0_cachetype;
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uint32_t c1_sys; /* System control register. */
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uint32_t c2_base; /* MMU translation table base. */
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uint32_t c3_faultstatus; /* Fault status registers. */
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uint32_t c4_faultaddr; /* Fault address registers. */
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uint32_t c5_cacheop; /* Cache operation registers. */
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uint32_t c6_tlbop; /* TLB operation registers. */
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} cp0;
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/* UniCore-F64 coprocessor state. */
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struct {
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float64 regs[16];
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uint32_t xregs[32];
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float_status fp_status;
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} ucf64;
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CPU_COMMON
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/* Internal CPU feature flags. */
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uint32_t features;
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} CPUUniCore32State;
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/**
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* UniCore32CPU:
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* @env: #CPUUniCore32State
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*
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* A UniCore32 CPU.
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*/
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struct UniCore32CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUUniCore32State env;
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};
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static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
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{
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return container_of(env, UniCore32CPU, env);
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}
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#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
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#define ENV_OFFSET offsetof(UniCore32CPU, env)
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void uc32_cpu_do_interrupt(CPUState *cpu);
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bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void uc32_cpu_dump_state(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#define ASR_M (0x1f)
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#define ASR_MODE_USER (0x10)
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#define ASR_MODE_INTR (0x12)
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#define ASR_MODE_PRIV (0x13)
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#define ASR_MODE_TRAP (0x17)
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#define ASR_MODE_EXTN (0x1b)
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#define ASR_MODE_SUSR (0x1f)
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#define ASR_I (1 << 7)
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#define ASR_V (1 << 28)
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#define ASR_C (1 << 29)
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#define ASR_Z (1 << 30)
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#define ASR_N (1 << 31)
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#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
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#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
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#define UC32_EXCP_PRIV (1)
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#define UC32_EXCP_ITRAP (2)
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#define UC32_EXCP_DTRAP (3)
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#define UC32_EXCP_INTR (4)
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/* Return the current ASR value. */
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target_ulong cpu_asr_read(CPUUniCore32State *env1);
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/* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
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void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
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/* UniCore-F64 system registers. */
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#define UC32_UCF64_FPSCR (31)
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#define UCF64_FPSCR_MASK (0x27ffffff)
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#define UCF64_FPSCR_RND_MASK (0x7)
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#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
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#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
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#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
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#define UCF64_FPSCR_FLAG_MASK (0x3ff)
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#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
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#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
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#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
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#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
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#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
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#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
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#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
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#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
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#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
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#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
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#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
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#define UC32_HWCAP_CMOV 4 /* 1 << 2 */
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#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
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#define cpu_signal_handler uc32_cpu_signal_handler
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int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
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{
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return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
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}
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#include "exec/cpu-all.h"
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#define cpu_init(cpu_model) cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)
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#define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
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#define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX
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static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->regs[31];
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*cs_base = 0;
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*flags = 0;
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if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
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*flags |= (1 << 6);
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}
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}
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int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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int mmu_idx);
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void uc32_translate_init(void);
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void switch_mode(CPUUniCore32State *, int);
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#endif /* UNICORE32_CPU_H */
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