qemu/target
Laurent Vivier 3f215a147b target/m68k: add DisasContext parameter to gen_extend()
This parameter will be needed to manage automatic release
of temporary allocated TCG variables.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180319113544.704-2-laurent@vivier.eu>
2018-03-20 09:38:51 +01:00
..
alpha target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
arm target/arm: Make 'any' CPU just an alias for 'max' 2018-03-09 17:09:44 +00:00
cris qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
hppa target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
i386 * Migrate MSR_SMI_COUNT (Liran) 2018-03-15 16:49:30 +00:00
lm32 qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
m68k target/m68k: add DisasContext parameter to gen_extend() 2018-03-20 09:38:51 +01:00
microblaze target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
mips qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
moxie target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
nios2 target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
openrisc target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
ppc PowerPC: Add TS bits into msr_mask 2018-03-06 13:16:29 +11:00
riscv RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
s390x target/s390x: Remove leading underscores from #defines 2018-03-08 15:49:23 +01:00
sh4 target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00
sparc sparc: fix leon3 casa instruction when MMU is disabled 2018-03-08 07:22:03 +00:00
tilegx qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
tricore tricore: renamed masking of PIE 2018-03-02 11:46:36 +01:00
unicore32 ui/curses: build as module 2018-03-05 08:44:11 +01:00
xtensa target/*/cpu.h: remove softfloat.h 2018-02-21 10:20:24 +00:00