edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
#ifndef SHPC_H
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#define SHPC_H
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#include "exec/memory.h"
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#include "hw/hotplug.h"
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#include "hw/pci/pci_device.h"
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#include "migration/vmstate.h"
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struct SHPCDevice {
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/* Capability offset in device's config space */
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int cap;
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/* # of hot-pluggable slots */
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int nslots;
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/* SHPC WRS: working register set */
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uint8_t *config;
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/* Used to enable checks on load. Note that writable bits are
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* never checked even if set in cmask. */
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uint8_t *cmask;
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/* Used to implement R/W bytes */
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uint8_t *wmask;
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/* Used to implement RW1C(Write 1 to Clear) bytes */
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uint8_t *w1cmask;
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/* MMIO for the SHPC BAR */
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MemoryRegion mmio;
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/* Bus controlled by this SHPC */
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PCIBus *sec_bus;
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/* MSI already requested for this event */
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int msi_requested;
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};
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void shpc_reset(PCIDevice *d);
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int shpc_bar_size(PCIDevice *dev);
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int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar,
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unsigned off, Error **errp);
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void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
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void shpc_free(PCIDevice *dev);
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void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
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void shpc_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp);
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void shpc_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp);
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void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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extern VMStateInfo shpc_vmstate_info;
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#define SHPC_VMSTATE(_field, _type, _test) \
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VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _type, _test, 0, \
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shpc_vmstate_info, 0)
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static inline bool shpc_present(const PCIDevice *dev)
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{
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return dev->cap_present & QEMU_PCI_CAP_SHPC;
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}
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#endif
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