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include/hw/pci: Split pci_device.h off pci.h

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PCIDeviceClass and PCIDevice are defined in pci.h.  Many users of the
header don't actually need them.  Similar structs live in their own
headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in
pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h,
PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and
PCIESlot in pcie_port.h.

Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with
the code that needs them.  Adjust include directives.

This also enables the next commit.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20221222100330.380143-6-armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Markus Armbruster 2022-12-22 11:03:28 +01:00 committed by Michael S. Tsirkin
parent 4a96b8cf49
commit edf5ca5dbe
93 changed files with 441 additions and 427 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/acpi/erst.c
View File

@ -14,7 +14,7 @@
#include "hw/qdev-core.h"
#include "exec/memory.h"
#include "qom/object.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qom/object_interfaces.h"
#include "qemu/error-report.h"
#include "migration/vmstate.h"

2
hw/audio/ac97.c
View File

@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "hw/audio/soundhw.h"
#include "audio/audio.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/module.h"

2
hw/audio/es1370.c
View File

@ -29,7 +29,7 @@
#include "qemu/osdep.h"
#include "hw/audio/soundhw.h"
#include "audio/audio.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/dma.h"

2
hw/audio/via-ac97.c
View File

@ -11,7 +11,7 @@
#include "qemu/osdep.h"
#include "hw/isa/vt82c686.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
static void via_ac97_realize(PCIDevice *pci_dev, Error **errp)
{

2
hw/char/serial-pci-multi.c
View File

@ -31,7 +31,7 @@
#include "qapi/error.h"
#include "hw/char/serial.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "migration/vmstate.h"

2
hw/char/serial-pci.c
View File

@ -30,7 +30,7 @@
#include "qemu/module.h"
#include "hw/char/serial.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qom/object.h"

1
hw/core/qdev-properties-system.c
View File

@ -32,6 +32,7 @@
#include "sysemu/blockdev.h"
#include "net/net.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie.h"
#include "util/block-helpers.h"
static bool check_prop_still_unset(Object *obj, const char *name,

2
hw/display/ati_int.h
View File

@ -10,7 +10,7 @@
#define ATI_INT_H
#include "qemu/timer.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/i2c/bitbang_i2c.h"
#include "vga_int.h"
#include "qom/object.h"

2
hw/display/bochs-display.c
View File

@ -8,7 +8,7 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/display/bochs-vbe.h"

2
hw/display/cirrus_vga.c
View File

@ -39,7 +39,7 @@
#include "sysemu/reset.h"
#include "qapi/error.h"
#include "trace.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "ui/pixel_ops.h"

3
hw/display/qxl.h
View File

@ -1,8 +1,7 @@
#ifndef HW_QXL_H
#define HW_QXL_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "vga_int.h"
#include "qemu/thread.h"

2
hw/display/sm501.c
View File

@ -32,7 +32,7 @@
#include "ui/console.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "hw/i2c/i2c.h"
#include "hw/display/i2c-ddc.h"

2
hw/display/vga-pci.c
View File

@ -25,7 +25,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "vga_int.h"

2
hw/display/vmware_vga.c
View File

@ -29,7 +29,7 @@
#include "qemu/log.h"
#include "hw/loader.h"
#include "trace.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qom/object.h"

2
hw/i386/xen/xen_pvdevice.c
View File

@ -32,7 +32,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "trace.h"

2
hw/ide/ahci_internal.h
View File

@ -26,7 +26,7 @@
#include "hw/ide/ahci.h"
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#define AHCI_MEM_BAR_SIZE 0x1000
#define AHCI_MAX_PORTS 32

2
hw/ipack/tpci200.c
View File

@ -12,7 +12,7 @@
#include "qemu/units.h"
#include "hw/ipack/ipack.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "migration/vmstate.h"
#include "qemu/bitops.h"
#include "qemu/module.h"

2
hw/ipmi/pci_ipmi_bt.c
View File

@ -25,7 +25,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "hw/ipmi/ipmi_bt.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define TYPE_PCI_IPMI_BT "pci-ipmi-bt"

2
hw/ipmi/pci_ipmi_kcs.c
View File

@ -25,7 +25,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "hw/ipmi/ipmi_kcs.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define TYPE_PCI_IPMI_KCS "pci-ipmi-kcs"

2
hw/isa/i82378.c
View File

@ -18,7 +18,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/irq.h"
#include "hw/intc/i8259.h"
#include "hw/timer/i8254.h"

2
hw/mips/gt64xxx_pci.c
View File

@ -26,7 +26,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "migration/vmstate.h"
#include "hw/intc/i8259.h"

2
hw/misc/pci-testdev.c
View File

@ -19,7 +19,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "qemu/event_notifier.h"
#include "qemu/module.h"

2
hw/misc/pvpanic-pci.c
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@ -20,7 +20,7 @@
#include "migration/vmstate.h"
#include "hw/misc/pvpanic.h"
#include "qom/object.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "standard-headers/linux/pvpanic.h"
OBJECT_DECLARE_SIMPLE_TYPE(PVPanicPCIState, PVPANIC_PCI_DEVICE)

2
hw/net/can/can_kvaser_pci.c
View File

@ -37,7 +37,7 @@
#include "qapi/error.h"
#include "chardev/char.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/can_emu.h"

2
hw/net/can/can_mioe3680_pci.c
View File

@ -33,7 +33,7 @@
#include "qapi/error.h"
#include "chardev/char.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/can_emu.h"

2
hw/net/can/can_pcm3680_pci.c
View File

@ -33,7 +33,7 @@
#include "qapi/error.h"
#include "chardev/char.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/can_emu.h"

2
hw/net/can/ctucan_pci.c
View File

@ -34,7 +34,7 @@
#include "qapi/error.h"
#include "chardev/char.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/can_emu.h"

2
hw/net/e1000.c
View File

@ -26,7 +26,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/eth.h"

2
hw/net/e1000x_common.c
View File

@ -24,7 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "net/net.h"
#include "e1000x_common.h"

2
hw/net/eepro100.c
View File

@ -42,7 +42,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/net.h"

2
hw/net/ne2000-pci.c
View File

@ -24,7 +24,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "ne2000.h"

2
hw/net/net_tx_pkt.c
View File

@ -21,7 +21,7 @@
#include "net/checksum.h"
#include "net/tap.h"
#include "net/net.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
enum {
NET_TX_PKT_VHDR_FRAG = 0,

2
hw/net/pcnet-pci.c
View File

@ -29,7 +29,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "net/net.h"

2
hw/net/rocker/rocker.c
View File

@ -16,7 +16,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "migration/vmstate.h"

2
hw/net/rocker/rocker_desc.c
View File

@ -16,7 +16,7 @@
#include "qemu/osdep.h"
#include "net/net.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "rocker.h"
#include "rocker_hw.h"

2
hw/net/rtl8139.c
View File

@ -53,7 +53,7 @@
#include "qemu/osdep.h"
#include <zlib.h>
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "sysemu/dma.h"

2
hw/net/sungem.c
View File

@ -8,7 +8,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/log.h"

2
hw/net/sunhme.c
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@ -23,7 +23,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/net/mii.h"

2
hw/net/tulip.c
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@ -9,7 +9,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/qdev-properties.h"
#include "hw/nvram/eeprom93xx.h"
#include "migration/vmstate.h"

2
hw/net/virtio-net.c
View File

@ -42,7 +42,7 @@
#include "sysemu/sysemu.h"
#include "trace.h"
#include "monitor/qdev.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "net_rx_pkt.h"
#include "hw/virtio/vhost.h"
#include "sysemu/qtest.h"

2
hw/net/vmxnet3_defs.h
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@ -19,7 +19,7 @@
#include "net/net.h"
#include "hw/net/vmxnet3.h"
#include "qom/object.h"
#include "hw/pci/pci_device.h"
#define TYPE_VMXNET3 "vmxnet3"
typedef struct VMXNET3State VMXNET3State;

2
hw/nvme/nvme.h
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@ -19,7 +19,7 @@
#define HW_NVME_NVME_H
#include "qemu/uuid.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/block/block.h"
#include "block/nvme.h"

2
hw/pci-host/bonito.c
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@ -42,7 +42,7 @@
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/irq.h"
#include "hw/mips/mips.h"
#include "hw/pci/pci_host.h"

2
hw/pci-host/dino.c
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@ -15,7 +15,7 @@
#include "qemu/units.h"
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/dino.h"

2
hw/pci-host/grackle.c
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@ -25,7 +25,7 @@
#include "qemu/osdep.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/irq.h"
#include "qapi/error.h"
#include "qemu/module.h"

2
hw/pci-host/mv64361.c
View File

@ -13,7 +13,7 @@
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "hw/irq.h"
#include "hw/intc/i8259.h"

2
hw/pci-host/ppce500.c
View File

@ -19,7 +19,7 @@
#include "hw/ppc/e500-ccsr.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "qemu/bswap.h"
#include "qemu/module.h"

2
hw/pci-host/raven.c
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@ -28,7 +28,7 @@
#include "qemu/units.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"

2
hw/pci-host/sh_pci.c
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@ -26,7 +26,7 @@
#include "hw/sysbus.h"
#include "hw/sh4/sh.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "qemu/bswap.h"
#include "qemu/module.h"

2
hw/pci-host/uninorth.c
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@ -26,7 +26,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qemu/module.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/uninorth.h"
#include "trace.h"

2
hw/pci-host/versatile.c
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@ -12,7 +12,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"

1
hw/pci/pci-hmp-cmds.c
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@ -15,6 +15,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "monitor/hmp.h"
#include "monitor/monitor.h"
#include "pci-internal.h"

2
hw/pci/pcie_host.c
View File

@ -20,7 +20,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie_host.h"
#include "qemu/module.h"

2
hw/pci/pcie_sriov.c
View File

@ -11,7 +11,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie.h"
#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"

2
hw/pci/slotid_cap.c
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@ -1,6 +1,6 @@
#include "qemu/osdep.h"
#include "hw/pci/slotid_cap.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qemu/error-report.h"
#include "qapi/error.h"

2
hw/ppc/ppc440_pcix.c
View File

@ -26,7 +26,7 @@
#include "hw/irq.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "trace.h"
#include "qom/object.h"

2
hw/ppc/ppc4xx_pci.c
View File

@ -29,7 +29,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/reset.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "trace.h"
#include "qom/object.h"

1
hw/ppc/spapr_pci_vfio.c
View File

@ -22,6 +22,7 @@
#include "hw/ppc/spapr.h"
#include "hw/pci-host/spapr.h"
#include "hw/pci/msix.h"
#include "hw/pci/pci_device.h"
#include "hw/vfio/vfio.h"
#include "qemu/error-report.h"

2
hw/rdma/rdma_utils.c
View File

@ -14,7 +14,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "trace.h"
#include "rdma_utils.h"

1
hw/rdma/vmw/pvrdma.h
View File

@ -19,6 +19,7 @@
#include "qemu/units.h"
#include "qemu/notify.h"
#include "hw/pci/msix.h"
#include "hw/pci/pci_device.h"
#include "chardev/char-fe.h"
#include "hw/net/vmxnet3_defs.h"

1
hw/s390x/s390-pci-inst.c
View File

@ -16,6 +16,7 @@
#include "exec/memory-internal.h"
#include "qemu/error-report.h"
#include "sysemu/hw_accel.h"
#include "hw/pci/pci_device.h"
#include "hw/s390x/s390-pci-inst.h"
#include "hw/s390x/s390-pci-bus.h"
#include "hw/s390x/s390-pci-kvm.h"

2
hw/scsi/esp-pci.c
View File

@ -24,7 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/irq.h"
#include "hw/nvram/eeprom93xx.h"
#include "hw/scsi/esp.h"

2
hw/scsi/lsi53c895a.c
View File

@ -16,7 +16,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/scsi/scsi.h"
#include "migration/vmstate.h"
#include "sysemu/dma.h"

2
hw/scsi/mptsas.h
View File

@ -2,7 +2,7 @@
#define MPTSAS_H
#include "mpi.h"
#include "qom/object.h"
#include "hw/pci/pci_device.h"
#define MPTSAS_NUM_PORTS 8
#define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */

1
hw/smbios/smbios.c
View File

@ -28,6 +28,7 @@
#include "hw/loader.h"
#include "hw/boards.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_device.h"
#include "smbios_build.h"
/* legacy structures and constants for <= 2.0 machines */

2
hw/usb/hcd-ehci.h
View File

@ -21,7 +21,7 @@
#include "qemu/timer.h"
#include "hw/usb.h"
#include "sysemu/dma.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/sysbus.h"
#ifndef EHCI_DEBUG

2
hw/usb/hcd-ohci-pci.c
View File

@ -23,7 +23,7 @@
#include "qemu/timer.h"
#include "hw/usb.h"
#include "migration/vmstate.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/sysbus.h"
#include "hw/qdev-dma.h"
#include "hw/qdev-properties.h"

2
hw/usb/hcd-uhci.h
View File

@ -30,7 +30,7 @@
#include "exec/memory.h"
#include "qemu/timer.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/usb.h"
typedef struct UHCIQueue UHCIQueue;

1
hw/usb/hcd-xhci-pci.h
View File

@ -24,6 +24,7 @@
#ifndef HW_USB_HCD_XHCI_PCI_H
#define HW_USB_HCD_XHCI_PCI_H
#include "hw/pci/pci_device.h"
#include "hw/usb.h"
#include "hcd-xhci.h"

2
hw/vfio/pci.h
View File

@ -13,7 +13,7 @@
#define HW_VFIO_VFIO_PCI_H
#include "exec/memory.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/vfio/vfio-common.h"
#include "qemu/event_notifier.h"
#include "qemu/queue.h"

2
hw/watchdog/wdt_i6300esb.c
View File

@ -24,7 +24,7 @@
#include "qemu/module.h"
#include "qemu/timer.h"
#include "sysemu/watchdog.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "migration/vmstate.h"
#include "qom/object.h"

2
include/hw/acpi/piix4.h
View File

@ -22,7 +22,7 @@
#ifndef HW_ACPI_PIIX4_H
#define HW_ACPI_PIIX4_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/memory_hotplug.h"

1
include/hw/arm/allwinner-a10.h
View File

@ -4,6 +4,7 @@
#include "qemu/error-report.h"
#include "hw/char/serial.h"
#include "hw/arm/boot.h"
#include "hw/pci/pci_device.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"

2
include/hw/cxl/cxl_device.h
View File

@ -11,7 +11,7 @@
#define CXL_DEVICE_H
#include "hw/cxl/cxl_component.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/register.h"
/*

2
include/hw/ide/pci.h
View File

@ -2,7 +2,7 @@
#define HW_IDE_PCI_H
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define BM_STATUS_DMAING 0x01

2
include/hw/misc/macio/macio.h
View File

@ -27,7 +27,7 @@
#define MACIO_H
#include "hw/char/escc.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/ide/internal.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"

2
include/hw/pci-host/gpex.h
View File

@ -22,7 +22,7 @@
#include "exec/hwaddr.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie_host.h"
#include "qom/object.h"

2
include/hw/pci-host/i440fx.h
View File

@ -11,7 +11,7 @@
#ifndef HW_PCI_I440FX_H
#define HW_PCI_I440FX_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci-host/pam.h"
#include "qom/object.h"

2
include/hw/pci-host/q35.h
View File

@ -22,7 +22,7 @@
#ifndef HW_Q35_H
#define HW_Q35_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci-host/pam.h"
#include "qemu/units.h"

2
include/hw/pci-host/sabre.h
View File

@ -1,7 +1,7 @@
#ifndef HW_PCI_HOST_SABRE_H
#define HW_PCI_HOST_SABRE_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "hw/sparc/sun4u_iommu.h"
#include "qom/object.h"

2
include/hw/pci/msi.h
View File

@ -21,7 +21,7 @@
#ifndef QEMU_MSI_H
#define QEMU_MSI_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
struct MSIMessage {
uint64_t address;

344
include/hw/pci/pci.h
View File

@ -166,7 +166,6 @@ enum {
#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
#include "hw/pci/pci_regs.h"
#include "hw/pci/pcie.h"
/* PCI HEADER_TYPE */
#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
@ -210,23 +209,6 @@ enum {
QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
typedef struct PCIDeviceClass PCIDeviceClass;
DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
PCI_DEVICE, TYPE_PCI_DEVICE)
/*
* Implemented by devices that can be plugged on CXL buses. In the spec, this is
* actually a "CXL Component, but we name it device to match the PCI naming.
*/
#define INTERFACE_CXL_DEVICE "cxl-device"
/* Implemented by devices that can be plugged on PCI Express buses */
#define INTERFACE_PCIE_DEVICE "pci-express-device"
/* Implemented by devices that can be plugged on Conventional PCI buses */
#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
typedef struct PCIINTxRoute {
enum {
PCI_INTX_ENABLED,
@ -236,24 +218,6 @@ typedef struct PCIINTxRoute {
int irq;
} PCIINTxRoute;
struct PCIDeviceClass {
DeviceClass parent_class;
void (*realize)(PCIDevice *dev, Error **errp);
PCIUnregisterFunc *exit;
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision;
uint16_t class_id;
uint16_t subsystem_vendor_id; /* only for header type = 0 */
uint16_t subsystem_id; /* only for header type = 0 */
const char *romfile; /* rom bar */
};
typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
MSIMessage msg);
@ -262,129 +226,6 @@ typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
unsigned int vector_start,
unsigned int vector_end);
enum PCIReqIDType {
PCI_REQ_ID_INVALID = 0,
PCI_REQ_ID_BDF,
PCI_REQ_ID_SECONDARY_BUS,
PCI_REQ_ID_MAX,
};
typedef enum PCIReqIDType PCIReqIDType;
struct PCIReqIDCache {
PCIDevice *dev;
PCIReqIDType type;
};
typedef struct PCIReqIDCache PCIReqIDCache;
struct PCIDevice {
DeviceState qdev;
bool partially_hotplugged;
bool has_power;
/* PCI config space */
uint8_t *config;
/*
* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask.
*/
uint8_t *cmask;
/* Used to implement R/W bytes */
uint8_t *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
uint8_t *w1cmask;
/* Used to allocate config space for capabilities. */
uint8_t *used;
/* the following fields are read only */
int32_t devfn;
/*
* Cached device to fetch requester ID from, to avoid the PCI tree
* walking every time we invoke PCI request (e.g., MSI). For
* conventional PCI root complex, this field is meaningless.
*/
PCIReqIDCache requester_id_cache;
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
MemoryRegion bus_master_container_region;
MemoryRegion bus_master_enable_region;
/* do not access the following fields */
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
/* Legacy PCI VGA regions */
MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
bool has_vga;
/* Current IRQ levels. Used internally by the generic PCI code. */
uint8_t irq_state;
/* Capability bits */
uint32_t cap_present;
/* Offset of MSI-X capability in config space */
uint8_t msix_cap;
/* MSI-X entries */
int msix_entries_nr;
/* Space to store MSIX table & pending bit array */
uint8_t *msix_table;
uint8_t *msix_pba;
/* May be used by INTx or MSI during interrupt notification */
void *irq_opaque;
MSITriggerFunc *msi_trigger;
MSIPrepareMessageFunc *msi_prepare_message;
MSIxPrepareMessageFunc *msix_prepare_message;
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
unsigned *msix_entry_used;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
int32_t version_id;
/* Offset of MSI capability in config space */
uint8_t msi_cap;
/* PCI Express */
PCIExpressDevice exp;
/* SHPC */
SHPCDevice *shpc;
/* Location of option rom */
char *romfile;
uint32_t romsize;
bool has_rom;
MemoryRegion rom;
uint32_t rom_bar;
/* INTx routing notifier */
PCIINTxRoutingNotifier intx_routing_notifier;
/* MSI-X notifiers */
MSIVectorUseNotifier msix_vector_use_notifier;
MSIVectorReleaseNotifier msix_vector_release_notifier;
MSIVectorPollNotifier msix_vector_poll_notifier;
/* ID of standby device in net_failover pair */
char *failover_pair_id;
uint32_t acpi_index;
};
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
@ -745,11 +586,6 @@ void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
void pci_set_irq(PCIDevice *pci_dev, int level);
static inline int pci_intx(PCIDevice *pci_dev)
{
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}
static inline void pci_irq_assert(PCIDevice *pci_dev)
{
pci_set_irq(pci_dev, 1);
@ -770,186 +606,6 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev)
pci_irq_deassert(pci_dev);
}
static inline int pci_is_cxl(const PCIDevice *d)
{
return d->cap_present & QEMU_PCIE_CAP_CXL;
}
static inline int pci_is_express(const PCIDevice *d)
{
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
}
static inline int pci_is_express_downstream_port(const PCIDevice *d)
{
uint8_t type;
if (!pci_is_express(d) || !d->exp.exp_cap) {
return 0;
}
type = pcie_cap_get_type(d);
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
}
static inline int pci_is_vf(const PCIDevice *d)
{
return d->exp.sriov_vf.pf != NULL;
}
static inline uint32_t pci_config_size(const PCIDevice *d)
{
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}
static inline uint16_t pci_get_bdf(PCIDevice *dev)
{
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
}
uint16_t pci_requester_id(PCIDevice *dev);
/* DMA access functions */
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
{
return &dev->bus_master_as;
}
/**
* pci_dma_rw: Read from or write to an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to read or write
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len,
DMADirection dir, MemTxAttrs attrs)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
dir, attrs);
}
/**
* pci_dma_read: Read from an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault). Called within RCU critical section.
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, buf, len,
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
/**
* pci_dma_write: Write to address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len,
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t *val, \
MemTxAttrs attrs) \
{ \
return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
} \
static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t val, \
MemTxAttrs attrs) \
{ \
return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
}
PCI_DMA_DEFINE_LDST(ub, b, 8);
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
#undef PCI_DMA_DEFINE_LDST
/**
* pci_dma_map: Map device PCI address space range into host virtual address
* @dev: #PCIDevice to be accessed
* @addr: address within that device's address space
* @plen: pointer to length of buffer; updated on return to indicate
* if only a subset of the requested range has been mapped
* @dir: indicates the transfer direction
*
* Return: A host pointer, or %NULL if the resources needed to
* perform the mapping are exhausted (in that case *@plen
* is set to zero).
*/
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
MEMTXATTRS_UNSPECIFIED);
}
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
DMADirection dir, dma_addr_t access_len)
{
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
}
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
int alloc_hint)
{
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
}
extern const VMStateDescription vmstate_pci_device;
#define VMSTATE_PCI_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
}
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT | VMS_POINTER, \
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
}
MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
void pci_set_power(PCIDevice *pci_dev, bool state);

2
include/hw/pci/pci_bridge.h
View File

@ -26,7 +26,7 @@
#ifndef QEMU_PCI_BRIDGE_H
#define QEMU_PCI_BRIDGE_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "hw/cxl/cxl.h"
#include "qom/object.h"

350
include/hw/pci/pci_device.h Normal file
View File

@ -0,0 +1,350 @@
#ifndef QEMU_PCI_DEVICE_H
#define QEMU_PCI_DEVICE_H
#include "hw/pci/pci.h"
#include "hw/pci/pcie.h"
#define TYPE_PCI_DEVICE "pci-device"
typedef struct PCIDeviceClass PCIDeviceClass;
DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
PCI_DEVICE, TYPE_PCI_DEVICE)
/*
* Implemented by devices that can be plugged on CXL buses. In the spec, this is
* actually a "CXL Component, but we name it device to match the PCI naming.
*/
#define INTERFACE_CXL_DEVICE "cxl-device"
/* Implemented by devices that can be plugged on PCI Express buses */
#define INTERFACE_PCIE_DEVICE "pci-express-device"
/* Implemented by devices that can be plugged on Conventional PCI buses */
#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
struct PCIDeviceClass {
DeviceClass parent_class;
void (*realize)(PCIDevice *dev, Error **errp);
PCIUnregisterFunc *exit;
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision;
uint16_t class_id;
uint16_t subsystem_vendor_id; /* only for header type = 0 */
uint16_t subsystem_id; /* only for header type = 0 */
const char *romfile; /* rom bar */
};
enum PCIReqIDType {
PCI_REQ_ID_INVALID = 0,
PCI_REQ_ID_BDF,
PCI_REQ_ID_SECONDARY_BUS,
PCI_REQ_ID_MAX,
};
typedef enum PCIReqIDType PCIReqIDType;
struct PCIReqIDCache {
PCIDevice *dev;
PCIReqIDType type;
};
typedef struct PCIReqIDCache PCIReqIDCache;
struct PCIDevice {
DeviceState qdev;
bool partially_hotplugged;
bool has_power;
/* PCI config space */
uint8_t *config;
/*
* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask.
*/
uint8_t *cmask;
/* Used to implement R/W bytes */
uint8_t *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
uint8_t *w1cmask;
/* Used to allocate config space for capabilities. */
uint8_t *used;
/* the following fields are read only */
int32_t devfn;
/*
* Cached device to fetch requester ID from, to avoid the PCI tree
* walking every time we invoke PCI request (e.g., MSI). For
* conventional PCI root complex, this field is meaningless.
*/
PCIReqIDCache requester_id_cache;
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
MemoryRegion bus_master_container_region;
MemoryRegion bus_master_enable_region;
/* do not access the following fields */
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
/* Legacy PCI VGA regions */
MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
bool has_vga;
/* Current IRQ levels. Used internally by the generic PCI code. */
uint8_t irq_state;
/* Capability bits */
uint32_t cap_present;
/* Offset of MSI-X capability in config space */
uint8_t msix_cap;
/* MSI-X entries */
int msix_entries_nr;
/* Space to store MSIX table & pending bit array */
uint8_t *msix_table;
uint8_t *msix_pba;
/* May be used by INTx or MSI during interrupt notification */
void *irq_opaque;
MSITriggerFunc *msi_trigger;
MSIPrepareMessageFunc *msi_prepare_message;
MSIxPrepareMessageFunc *msix_prepare_message;
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
unsigned *msix_entry_used;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
int32_t version_id;
/* Offset of MSI capability in config space */
uint8_t msi_cap;
/* PCI Express */
PCIExpressDevice exp;
/* SHPC */
SHPCDevice *shpc;
/* Location of option rom */
char *romfile;
uint32_t romsize;
bool has_rom;
MemoryRegion rom;
uint32_t rom_bar;
/* INTx routing notifier */
PCIINTxRoutingNotifier intx_routing_notifier;
/* MSI-X notifiers */
MSIVectorUseNotifier msix_vector_use_notifier;
MSIVectorReleaseNotifier msix_vector_release_notifier;
MSIVectorPollNotifier msix_vector_poll_notifier;
/* ID of standby device in net_failover pair */
char *failover_pair_id;
uint32_t acpi_index;
};
static inline int pci_intx(PCIDevice *pci_dev)
{
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}
static inline int pci_is_cxl(const PCIDevice *d)
{
return d->cap_present & QEMU_PCIE_CAP_CXL;
}
static inline int pci_is_express(const PCIDevice *d)
{
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
}
static inline int pci_is_express_downstream_port(const PCIDevice *d)
{
uint8_t type;
if (!pci_is_express(d) || !d->exp.exp_cap) {
return 0;
}
type = pcie_cap_get_type(d);
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
}
static inline int pci_is_vf(const PCIDevice *d)
{
return d->exp.sriov_vf.pf != NULL;
}
static inline uint32_t pci_config_size(const PCIDevice *d)
{
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}
static inline uint16_t pci_get_bdf(PCIDevice *dev)
{
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
}
uint16_t pci_requester_id(PCIDevice *dev);
/* DMA access functions */
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
{
return &dev->bus_master_as;
}
/**
* pci_dma_rw: Read from or write to an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to read or write
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len,
DMADirection dir, MemTxAttrs attrs)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
dir, attrs);
}
/**
* pci_dma_read: Read from an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault). Called within RCU critical section.
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, buf, len,
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
/**
* pci_dma_write: Write to address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len,
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t *val, \
MemTxAttrs attrs) \
{ \
return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
} \
static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t val, \
MemTxAttrs attrs) \
{ \
return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
}
PCI_DMA_DEFINE_LDST(ub, b, 8);
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
#undef PCI_DMA_DEFINE_LDST
/**
* pci_dma_map: Map device PCI address space range into host virtual address
* @dev: #PCIDevice to be accessed
* @addr: address within that device's address space
* @plen: pointer to length of buffer; updated on return to indicate
* if only a subset of the requested range has been mapped
* @dir: indicates the transfer direction
*
* Return: A host pointer, or %NULL if the resources needed to
* perform the mapping are exhausted (in that case *@plen
* is set to zero).
*/
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
MEMTXATTRS_UNSPECIFIED);
}
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
DMADirection dir, dma_addr_t access_len)
{
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
}
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
int alloc_hint)
{
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
}
extern const VMStateDescription vmstate_pci_device;
#define VMSTATE_PCI_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
}
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT | VMS_POINTER, \
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
}
#endif

1
include/hw/pci/pcie_port.h
View File

@ -23,6 +23,7 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define TYPE_PCIE_PORT "pcie-port"

2
include/hw/pci/shpc.h
View File

@ -3,7 +3,7 @@
#include "exec/memory.h"
#include "hw/hotplug.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "migration/vmstate.h"
struct SHPCDevice {

2
include/hw/remote/iohub.h
View File

@ -11,7 +11,7 @@
#ifndef REMOTE_IOHUB_H
#define REMOTE_IOHUB_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qemu/event_notifier.h"
#include "qemu/thread-posix.h"
#include "hw/remote/mpqemu-link.h"

2
include/hw/remote/proxy.h
View File

@ -9,7 +9,7 @@
#ifndef PROXY_H
#define PROXY_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "io/channel.h"
#include "hw/remote/proxy-memory-listener.h"
#include "qemu/event_notifier.h"

2
include/hw/sd/sdhci.h
View File

@ -25,7 +25,7 @@
#ifndef SDHCI_H
#define SDHCI_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/sysbus.h"
#include "hw/sd/sd.h"
#include "qom/object.h"

3
include/hw/southbridge/piix.h
View File

@ -12,8 +12,7 @@
#ifndef HW_SOUTHBRIDGE_PIIX_H
#define HW_SOUTHBRIDGE_PIIX_H
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/pci/pci_device.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60

2
include/hw/xen/xen_common.h
View File

@ -15,7 +15,7 @@
#include "hw/xen/interface/io/xenbus.h"
#include "hw/xen/xen.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/xen/trace.h"
extern xc_interface *xen_xc;

1
tests/qtest/fuzz/generic_fuzz.c
View File

@ -24,6 +24,7 @@
#include "exec/ramblock.h"
#include "hw/qdev-core.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/boards.h"
#include "generic_fuzz_configs.h"
#include "hw/mem/sparse-mem.h"

2
ui/util.c
View File

@ -17,7 +17,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "qapi/error.h"
#include "ui/console.h"