345b7a8757
Division may (optionally) raise a division exception. Since the linux kernel has been prepared for this for some time, enable it by default. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-42-richard.henderson@linaro.org>
279 lines
7.0 KiB
C
279 lines
7.0 KiB
C
/*
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* Altera Nios II virtual CPU header
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef NIOS2_CPU_H
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#define NIOS2_CPU_H
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#include "exec/cpu-defs.h"
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#include "qom/object.h"
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typedef struct CPUArchState CPUNios2State;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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#endif
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#define TYPE_NIOS2_CPU "nios2-cpu"
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OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
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/**
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* Nios2CPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* A Nios2 CPU model.
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*/
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struct Nios2CPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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#define TARGET_HAS_ICE 1
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/* Configuration options for Nios II */
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#define RESET_ADDRESS 0x00000000
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#define EXCEPTION_ADDRESS 0x00000004
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#define FAST_TLB_MISS_ADDRESS 0x00000008
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#define NUM_GP_REGS 32
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#define NUM_CR_REGS 32
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/* General purpose register aliases */
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enum {
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R_ZERO = 0,
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R_AT = 1,
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R_RET0 = 2,
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R_RET1 = 3,
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R_ARG0 = 4,
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R_ARG1 = 5,
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R_ARG2 = 6,
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R_ARG3 = 7,
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R_ET = 24,
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R_BT = 25,
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R_GP = 26,
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R_SP = 27,
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R_FP = 28,
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R_EA = 29,
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R_BA = 30,
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R_RA = 31,
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};
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/* Control register aliases */
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enum {
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CR_STATUS = 0,
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CR_ESTATUS = 1,
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CR_BSTATUS = 2,
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CR_IENABLE = 3,
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CR_IPENDING = 4,
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CR_CPUID = 5,
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CR_EXCEPTION = 7,
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CR_PTEADDR = 8,
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CR_TLBACC = 9,
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CR_TLBMISC = 10,
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CR_ENCINJ = 11,
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CR_BADADDR = 12,
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CR_CONFIG = 13,
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CR_MPUBASE = 14,
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CR_MPUACC = 15,
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};
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FIELD(CR_STATUS, PIE, 0, 1)
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FIELD(CR_STATUS, U, 1, 1)
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FIELD(CR_STATUS, EH, 2, 1)
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FIELD(CR_STATUS, IH, 3, 1)
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FIELD(CR_STATUS, IL, 4, 6)
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FIELD(CR_STATUS, CRS, 10, 6)
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FIELD(CR_STATUS, PRS, 16, 6)
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FIELD(CR_STATUS, NMI, 22, 1)
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FIELD(CR_STATUS, RSIE, 23, 1)
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#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK
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#define CR_STATUS_U R_CR_STATUS_U_MASK
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#define CR_STATUS_EH R_CR_STATUS_EH_MASK
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#define CR_STATUS_IH R_CR_STATUS_IH_MASK
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#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK
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#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK
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FIELD(CR_EXCEPTION, CAUSE, 2, 5)
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FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
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FIELD(CR_PTEADDR, VPN, 2, 20)
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FIELD(CR_PTEADDR, PTBASE, 22, 10)
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FIELD(CR_TLBACC, PFN, 0, 20)
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FIELD(CR_TLBACC, G, 20, 1)
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FIELD(CR_TLBACC, X, 21, 1)
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FIELD(CR_TLBACC, W, 22, 1)
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FIELD(CR_TLBACC, R, 23, 1)
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FIELD(CR_TLBACC, C, 24, 1)
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FIELD(CR_TLBACC, IG, 25, 7)
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#define CR_TLBACC_C R_CR_TLBACC_C_MASK
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#define CR_TLBACC_R R_CR_TLBACC_R_MASK
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#define CR_TLBACC_W R_CR_TLBACC_W_MASK
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#define CR_TLBACC_X R_CR_TLBACC_X_MASK
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#define CR_TLBACC_G R_CR_TLBACC_G_MASK
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FIELD(CR_TLBMISC, D, 0, 1)
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FIELD(CR_TLBMISC, PERM, 1, 1)
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FIELD(CR_TLBMISC, BAD, 2, 1)
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FIELD(CR_TLBMISC, DBL, 3, 1)
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FIELD(CR_TLBMISC, PID, 4, 14)
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FIELD(CR_TLBMISC, WE, 18, 1)
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FIELD(CR_TLBMISC, RD, 19, 1)
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FIELD(CR_TLBMISC, WAY, 20, 4)
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FIELD(CR_TLBMISC, EE, 24, 1)
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#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK
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#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK
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#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK
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#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK
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#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK
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#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK
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#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK
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/* Exceptions */
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#define EXCP_BREAK 0x1000
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#define EXCP_SEMIHOST 0x1001
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#define EXCP_RESET 0
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#define EXCP_PRESET 1
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#define EXCP_IRQ 2
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#define EXCP_TRAP 3
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#define EXCP_UNIMPL 4
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#define EXCP_ILLEGAL 5
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#define EXCP_UNALIGN 6
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#define EXCP_UNALIGND 7
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#define EXCP_DIV 8
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#define EXCP_SUPERA_X 9
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#define EXCP_SUPERI 10
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#define EXCP_SUPERA_D 11
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#define EXCP_TLB_X 12
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#define EXCP_TLB_D (0x1000 | EXCP_TLB_X)
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#define EXCP_PERM_X 13
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#define EXCP_PERM_R 14
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#define EXCP_PERM_W 15
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#define EXCP_MPUI 16
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#define EXCP_MPUD 17
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struct CPUArchState {
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uint32_t regs[NUM_GP_REGS];
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uint32_t ctrl[NUM_CR_REGS];
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uint32_t pc;
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#if !defined(CONFIG_USER_ONLY)
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Nios2MMU mmu;
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#endif
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int error_code;
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};
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typedef struct {
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uint32_t writable;
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uint32_t readonly;
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} ControlRegState;
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/**
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* Nios2CPU:
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* @env: #CPUNios2State
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*
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* A Nios2 CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUNios2State env;
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bool diverr_present;
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bool mmu_present;
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uint32_t pid_num_bits;
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uint32_t tlb_num_ways;
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uint32_t tlb_num_entries;
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/* Addresses that are hard-coded in the FPGA build settings */
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uint32_t reset_addr;
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uint32_t exception_addr;
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uint32_t fast_tlb_miss_addr;
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/* Bits within each control register which are reserved or readonly. */
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ControlRegState cr_state[NUM_CR_REGS];
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};
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static inline bool nios2_cr_reserved(const ControlRegState *s)
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{
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return (s->writable | s->readonly) == 0;
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}
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void nios2_tcg_init(void);
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void nios2_cpu_do_interrupt(CPUState *cs);
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void dump_mmu(CPUNios2State *env);
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void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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void do_nios2_semihosting(CPUNios2State *env);
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#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
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#define cpu_gen_code cpu_nios2_gen_code
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_SUPERVISOR_IDX 0
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
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{
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return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
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MMU_SUPERVISOR_IDX;
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}
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#ifndef CONFIG_USER_ONLY
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bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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#endif
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typedef CPUNios2State CPUArchState;
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typedef Nios2CPU ArchCPU;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
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}
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#endif /* NIOS2_CPU_H */
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