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target/nios2: Support division error exception

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Division may (optionally) raise a division exception.
Since the linux kernel has been prepared for this for
some time, enable it by default.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-42-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:17:12 -07:00
parent e8d12542ee
commit 345b7a8757
7 changed files with 62 additions and 40 deletions
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4
linux-user/nios2/cpu_loop.c
View File

@ -38,6 +38,10 @@ void cpu_loop(CPUNios2State *env)
/* just indicate that signals should be handled asap */
break;
case EXCP_DIV:
force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
break;
case EXCP_TRAP:
/*
* TODO: This advance should be done in the translator, as

1
target/nios2/cpu.c
View File

@ -263,6 +263,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
static Property nios2_properties[] = {
DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true),
DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
/* ALTR,pid-num-bits */
DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),

2
target/nios2/cpu.h
View File

@ -207,7 +207,9 @@ struct ArchCPU {
CPUNegativeOffsetState neg;
CPUNios2State env;
bool diverr_present;
bool mmu_present;
uint32_t pid_num_bits;
uint32_t tlb_num_ways;
uint32_t tlb_num_entries;

4
target/nios2/helper.c
View File

@ -119,6 +119,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_UNALIGND:
name = "Misaligned (destination)";
break;
case EXCP_DIV:
name = "DIV error";
break;
case EXCP_TRAP:
name = "TRAP insn";
break;
@ -187,6 +190,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_SUPERI:
case EXCP_ILLEGAL:
case EXCP_DIV:
case EXCP_TRAP:
do_exception(cpu, cpu->exception_addr, 0, false);
break;

2
target/nios2/helper.h
View File

@ -19,6 +19,8 @@
*/
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, s32, env, s32, s32)
DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_3(eret, noreturn, env, i32, i32)

29
target/nios2/op_helper.c
View File

@ -31,6 +31,35 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
cpu_loop_exit(cs);
}
static void maybe_raise_div(CPUNios2State *env, uintptr_t ra)
{
Nios2CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
if (cpu->diverr_present) {
cs->exception_index = EXCP_DIV;
cpu_loop_exit_restore(cs, ra);
}
}
int32_t helper_divs(CPUNios2State *env, int32_t num, int32_t den)
{
if (unlikely(den == 0) || unlikely(den == -1 && num == INT32_MIN)) {
maybe_raise_div(env, GETPC());
return num; /* undefined */
}
return num / den;
}
uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den)
{
if (unlikely(den == 0)) {
maybe_raise_div(env, GETPC());
return num; /* undefined */
}
return num / den;
}
#ifndef CONFIG_USER_ONLY
void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
{

60
target/nios2/translate.c
View File

@ -654,59 +654,39 @@ gen_r_shift_s(ror, rotr_tl)
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
TCGv dest;
/* Stores into R_ZERO are ignored */
if (unlikely(instr.c == R_ZERO)) {
return;
if (instr.c == R_ZERO) {
dest = tcg_temp_new();
} else {
dest = cpu_R[instr.c];
}
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
gen_helper_divs(dest, cpu_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
tcg_gen_ext32s_tl(t0, load_gpr(dc, instr.a));
tcg_gen_ext32s_tl(t1, load_gpr(dc, instr.b));
tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_div_tl(cpu_R[instr.c], t0, t1);
tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]);
tcg_temp_free(t3);
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
if (instr.c == R_ZERO) {
tcg_temp_free(dest);
}
}
static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
TCGv dest;
/* Stores into R_ZERO are ignored */
if (unlikely(instr.c == R_ZERO)) {
return;
if (instr.c == R_ZERO) {
dest = tcg_temp_new();
} else {
dest = cpu_R[instr.c];
}
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
gen_helper_divu(dest, cpu_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a));
tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b));
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_tl(cpu_R[instr.c], t0, t1);
tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]);
tcg_temp_free(t3);
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
if (instr.c == R_ZERO) {
tcg_temp_free(dest);
}
}
static void trap(DisasContext *dc, uint32_t code, uint32_t flags)