Richard Henderson 3ceeb19a53 target/riscv: Introduce helper_set_rounding_mode_chkfrm ... The new helper always validates the contents of FRM, even if the new rounding mode is not DYN. This is required by the vector unit. Track whether we've validated FRM separately from whether we've updated fp_status with a given rounding mode, so that we can elide calls correctly. This partially reverts d6c4d3f2a6 which attempted the to do the same thing, but with two calls to gen_set_rm(), which is both inefficient and tickles an assertion in decode_save_opc. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-20 10:14:14 +10:00
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trans_privileged.c.inc	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvb.c.inc	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
trans_rvd.c.inc	target/riscv: add support for zdinx	2022-03-03 13:14:50 +10:00
trans_rvf.c.inc	target/riscv: add support for zfinx	2022-03-03 13:14:50 +10:00
trans_rvh.c.inc	target/riscv: Minimize the calls to decode_save_opc	2022-07-03 10:03:20 +10:00
trans_rvi.c.inc	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2022-06-10 09:31:42 +10:00
trans_rvv.c.inc	target/riscv: Introduce helper_set_rounding_mode_chkfrm	2023-01-20 10:14:14 +10:00
trans_rvzawrs.c.inc	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
trans_svinval.c.inc	target/riscv: add support for svinval extension	2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00